US2021143275A1PendingUtilityA1

Finfet stack gate memory and mehod of forming thereof

Assignee: INTEGRATED SILICON SOLUTION INCPriority: Nov 11, 2019Filed: Mar 11, 2020Published: May 13, 2021
Est. expiryNov 11, 2039(~13.3 yrs left)· nominal 20-yr term from priority
H10W 10/17H10W 10/014H10D 30/024H10D 30/6211H10B 41/30H10D 30/0413H10D 30/0411H10D 30/69H10D 30/68H01L 29/7851H01L 29/792H01L 21/76224H01L 29/66825H01L 29/66795H01L 29/66833H01L 29/788
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Claims

Abstract

A method of forming a FinFET stack gate memory includes a nitride film forming step, a nitride film is formed on a memory cell area with a shallow trench isolation (STI) structure; a stripping step, a portion of the nitride film is stripped, the other portion of the nitride film is remained at the STI structure, and a STI oxide is disposed in the STI structure; a floating gate (FG) structure forming step, a tunnel oxide is disposed, and a first polysilicon is disposed to form a FG structure; an oxide-nitride-oxide (ONO) layer disposing step, a portion of the STI oxide is stripped, and an ONO layer is disposed; a removing step, a portion of the ONO layer is removed; a control gate (CG) structure forming step, a portion of the FG structure is removed, and a second polysilicon is disposed to form a CG structure.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of forming a FinFET stack gate memory, comprising:
 a nitride film forming step, wherein a nitride film is formed on a memory cell area of a memory structure with a shallow trench isolation (STI) structure;   a stripping step, wherein a portion of the nitride film is stripped, the other portion of the nitride film which is unstripped is below a surface of a substrate and is remained at a bottom of the STI structure, and a STI oxide is disposed in the STI structure;   a floating gate (FG) structure forming step, wherein a tunnel oxide is disposed on the surface of the substrate and a surface of the other portion of the nitride film, and a first polysilicon is disposed on the tunnel oxide in the memory cell area and on the surface of the substrate in a non-memory cell area of the memory structure to form a FG structure;   an oxide-nitride-oxide (ONO) layer disposing step, wherein a portion of the STI oxide is stripped, and an ONO layer is disposed on a surface of the FG structure, the surface of the other portion of the nitride film, and a surface of the other portion of the STI oxide which is unstripped after a portion of the STI oxide is stripped in the memory cell area;   a removing step, wherein a portion of the ONO layer is removed in the non-memory cell area of the memory structure; and   a control gate (CG) structure forming step, wherein a portion of the FG structure is removed in the non-memory cell area of the memory structure, a second polysilicon is disposed on a surface of the ONO layer in the memory cell area and on the surface of the substrate and a surface of the STI oxide in the non-memory cell area of the memory structure to form a CG structure, and the FinFET stack gate memory is formed.   
     
     
         2 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the nitride film is made of a silicon nitride. 
     
     
         3 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the substrate is made of a silicon. 
     
     
         4 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the portion of the nitride film is stripped to 300 Å to 1400 Å in the stripping step. 
     
     
         5 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the portion of the STI oxide is stripped via a solution containing a hydrofluoric acid in the ONO layer disposing step. 
     
     
         6 . The method of forming the FinFET stack gate memory of  claim 1 , wherein a portion of the FG structure is removed by an etching process before the CG structure forming step. 
     
     
         7 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the nitride film in the non-memory cell area of the memory structure is removed by an etching process in the nitride film forming step. 
     
     
         8 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the STI oxide is disposed in the STI structure via a process of chemical vapor deposition (CVD) in the stripping step. 
     
     
         9 . The method of forming the FinFET stack gate memory of  claim 1 , wherein the FG structure is performed via a chemical-mechanical polishing (CMP) to form a FIN-shaped FG structure in the FG structure forming step. 
     
     
         10 . A FinFET stack gate memory, comprising:
 a substrate;   a shallow trench isolation (STI) structure, disposed on the substrate, and comprising:
 a STI oxide, disposed in the STI structure; and 
   a memory cell area, comprising:
 a nitride film, disposed on a surface of the STI structure and below the surface of the substrate; 
 a floating gate (FG) structure, disposed on the tunnel oxide; 
 an oxide-nitride-oxide (ONO) layer, disposed on the FG structure and the STI oxide, and the STI oxide located between the ONO layer and the nitride film; and 
 a control gate (CG) structure, disposed on the ONO layer, and the ONO layer located between the FG structure and the CG structure. 
   
     
     
         11 . The FinFET stack gate memory of  claim 10 , further comprising:
 a non-memory cell area, connecting to the memory cell area, and comprising a plurality of peripheral devices.   
     
     
         12 . The FinFET stack gate memory of  claim 11 , wherein the peripheral devices comprise a high voltage N-channel (HVN) logic device, a high voltage P-channel (HVP) logic device, a low voltage N-channel (LVN) logic device and a low voltage P-channel (LVP) logic device. 
     
     
         13 . The FinFET stack gate memory of  claim 10 , wherein the STI oxide is made of silicon oxide, and a thickness of the STI oxide is 600 Å to 2400 Å. 
     
     
         14 . The FinFET stack gate memory of  claim 10 , wherein the tunnel oxide is made of silicon oxide, and a thickness of the tunnel oxide is 70 Å to 105 Å. 
     
     
         15 . The FinFET stack gate memory of  claim 10 , wherein the ONO layer is made of silicon oxide/silicon nitride/silicon oxide, silicon oxide/alumina/silicon oxide, silicon oxide/zirconia/silicon oxide, silicon oxide/hafnia/silicon oxide, silicon oxide/titania/silicon oxide or silicon oxide/strontium titanate/silicon oxide.

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