Speech recognition circuit and method

Abstract

A speech recognition circuit comprising a circuit for providing state identifiers which identify states corresponding to nodes or groups of adjacent nodes in a lexical tree, and for providing scores corresponding to the state identifiers, the lexical tree comprising a model of words. The circuit includes: a memory structure for receiving and storing state identifiers identified by a node identifier identifying a node or group of adjacent nodes, the memory structure being adapted to allow lookup to identify particular state identifiers, reading of the scores corresponding to the state identifiers, and writing back of the scores to the memory structure after modification of the scores; an accumulator for receiving score updates corresponding to particular state identifiers from a score update generating circuit which generates the score updates using audio input, for receiving scores from the memory structure, and for modifying said scores by adding said score updates to said scores; and a selector circuit for selecting at least one node or group of adjacent nodes of the lexical tree according to said scores.

1 - 9 . (canceled) 
     
     
         10 . A speech recognition system, comprising:
 a microphone configured to output audio data;   a front end unit configured to produce a plurality of feature vectors based on a spectral analysis of frames of the audio data;   an accelerator configured to, for each of the plurality of feature vectors, determine a numerical value representing a probability that a frame of the audio data corresponding to the each of the plurality of feature vectors matches with a state of an acoustic model; and   at least one processor configured to:
 receive the numerical values; 
 detect, using a neural network, at least one word associated with the audio data based on the numerical values, wherein:
 the front end unit is physically distinct from the at least one processor, and 
 the front end unit and the at least one processor are formed on a single integrated circuit. 
 
   
     
     
         11 . The speech recognition system of  claim 10 , wherein at least one of the numerical values comprises a logarithm of a probability. 
     
     
         12 . The speech recognition system of  claim 10 , wherein operations of the front end unit, the accelerator, and the at least one processor are pipelined. 
     
     
         13 . The speech recognition system of  claim 10 , wherein the accelerator is configured to compute at least one of probabilities or logarithms of probabilities for Gaussian Distributions based on vectors of a second category of numerical values representing a mean and vectors of a third category of numerical values representing a variance. 
     
     
         14 . The speech recognition system of  claim 10 , further comprising a first buffer configured to store the plurality of feature vectors. 
     
     
         15 . The speech recognition system of  claim 14 , wherein the first buffer comprises an elastic buffer. 
     
     
         16 . The speech recognition system of  claim 14 , further comprising a second buffer configured to store the numerical values. 
     
     
         17 . The speech recognition system of  claim 16 , wherein the second buffer comprises an elastic buffer. 
     
     
         18 . The speech recognition system of  claim 10 , wherein the acoustic model comprises a first acoustic model for English and a second acoustic model for a language different from English. 
     
     
         19 . The speech recognition system of  claim 10 , wherein the acoustic model is stored in a compressed form. 
     
     
         20 . The speech recognition system of  claim 10 , wherein at least one state of the acoustic model represents a triphone. 
     
     
         21 . The speech recognition system of  claim 10 , wherein the front end unit signals to the accelerator or the at least one processor when at least one of the plurality of feature vectors is available for processing. 
     
     
         22 . The speech recognition system of  claim 21 , wherein the accelerator raises an interrupt to the at least one processor when the accelerator produces a numerical value for a frame. 
     
     
         23 . The speech recognition system of  claim 22 , wherein the numerical values are written to a memory by direct memory access (DMA). 
     
     
         24 . The speech recognition system of  claim 10 , further comprising a battery configured to power the front end unit, the accelerator, and the at least one processor. 
     
     
         25 . The speech recognition system of  claim 10 , further comprising a push-to-dictate button. 
     
     
         26 . A mobile phone comprising the speech recognition system of  claim 10 . 
     
     
         27 . An electronic entertainment product comprising the speech recognition system of  claim 10 . 
     
     
         28 . An appliance comprising the speech recognition system of  claim 10 . 
     
     
         29 . A vehicle comprising the speech recognition system of  claim 10 . 
     
     
         30 . A desktop, laptop or tablet personal computer comprising the speech recognition system of  claim 10 . 
     
     
         31 . A server computer comprising the speech recognition system of  claim 10 .