Chemfet array

Abstract

An array of pixels, wherein each pixel comprises: a CHEMFET sensor; and a sigma delta ADC.

1 . An array of pixels, wherein each pixel comprises:
 a CHEMFET sensor; and   a sigma delta ADC.   
     
     
         2 . The array of pixels according to  claim 1 , wherein the CHEMFET sensor is an ISFET sensor. 
     
     
         3 . The array of pixels according to  claim 1 , wherein the sigma delta ADC is a single ended first order sigma delta ADC. 
     
     
         4 . The array of pixels according to  claim 1 , wherein each pixel further comprises bias control. 
     
     
         5 . The array of pixels according to  claim 1 , wherein each pixel has an area in the region of 100 μm×100 μm. 
     
     
         6 . The array of pixels according to  claim 1 , wherein the array comprises in the region of 4000 pixels. 
     
     
         7 . The array of pixels according to  claim 1 , wherein each pixel further comprises a switch configured to control the flow of data from the pixel. 
     
     
         8 . A chip comprising:
 an array of pixels according to  claim 2 , and   a clocking arrangement comprising:
 a first clock signal common to all of the pixels in the array, for sampling the ISFET signal; and 
 a second clock signal provided sequentially across the array, for conversion of the signal. 
   
     
     
         9 . The chip according to  claim 8 , further comprising control signals for each pixel that enable the ISFET and the ADC within each pixel to be switched on only when required. 
     
     
         10 . A device comprising an array of wells each configured to receive a biological or chemical substance, wherein the array of wells is provided over a chip according to  claim 8 . 
     
     
         11 . The device according to  claim 10 , wherein each well covers more than one pixel. 
     
     
         12 . The array of pixels according to  claim 2 , wherein the sigma delta ADC is a single ended first order sigma delta ADC. 
     
     
         13 . The array of pixels according to  claim 12 , wherein each pixel further comprises bias control. 
     
     
         14 . The array of pixels according to  claim 13 , wherein each pixel has an area in the region of 100 μm×100 m. 
     
     
         15 . The array of pixels according to  claim 14 , wherein the array comprises in the region of 4000 pixels. 
     
     
         16 . The array of pixels according to  claim 15 , wherein each pixel further comprises a switch configured to control the flow of data from the pixel. 
     
     
         17 . The array of pixels according to  claim 13 , wherein each pixel further comprises a switch configured to control the flow of data from the pixel.