TVS Diode and Assembly Having Asymmetric Breakdown Voltage

Abstract

In one embodiment, an asymmetric TVS device may include a semiconductor substrate, comprising an inner region, the inner region having a first polarity, and a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity. The asymmetric TVS device may also include a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface, wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.

What is claimed is: 
     
         1 . An asymmetric transient voltage suppression (TVS) device, comprising:
 a semiconductor substrate, the semiconductor substrate comprising an inner region, the inner region having a first polarity;   a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity, opposite the first polarity; and   a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface,   wherein the first surface region comprises a first dopant concentration, and wherein the second surface region comprises a second dopant concentration, greater than the first dopant concentration.   
     
     
         2 . The asymmetric TVS device of  claim 1 , the inner region having an N-type polarity. 
     
     
         3 . The asymmetric TVS device of  claim 1 , wherein the inner region and first surface region comprise a first TVS diode, having a first breakdown voltage, and wherein the inner region and the second surface region comprise a second TVS diode of opposite polarity to the first TVS diode, and having a second breakdown voltage, different from the first breakdown voltage. 
     
     
         4 . The asymmetric TVS device of  claim 3 , the first breakdown voltage being in a range of 15V to 20 V, and the second breakdown voltage being in a range of 30 V to 35 V. 
     
     
         5 . The asymmetric TVS device of  claim 1 , the first dopant concentration comprising a range of 8E19/cm 3 , and the second dopant concentration comprising 2E19/cm 3 . 
     
     
         6 . The asymmetric TVS device of  claim 1 , the first surface region comprising a first surface area, the second surface region comprising a second surface area, the same as the first surface area. 
     
     
         7 . A method of forming an asymmetric transient voltage suppression (TVS) device, comprising:
 providing a semiconductor substrate, the semiconductor substrate comprising a first dopant of a first polarity, and defining a first surface and a second surface, opposite the first surface;   performing a first oxidation process of the semiconductor substrate, wherein a first oxide layer forms on the first surface and a second oxide layer forms on the second surface;   removing the first oxide layer from at least a first region of the first surface of the semiconductor substrate;   performing a first doping process, wherein the first doping process generates a first surface region on the first surface, having a first concentration of a second dopant of second polarity, opposite the first polarity;   performing a second oxidation process of the semiconductor substrate, wherein a third oxide layer forms over the first region on the first surface;   removing the second oxide layer from at least a second region of the second surface; and   performing a second doping process, wherein the second doping process generates a second surface region on the second surface, having a second concentration of a second dopant of second polarity, greater than the first concentration.   
     
     
         8 . The method of  claim 7 , wherein the semiconductor substrate comprises an n-type polarity, and wherein the first surface region and the second surface region comprise a p-type polarity. 
     
     
         9 . The method of  claim 8 , wherein the semiconductor substrate comprises an n-type inner region, characterized by the n-type polarity, after the performing the first doping process and the performing the second doping process. 
     
     
         10 . The method of  claim 9 , wherein the n-type inner region and first surface region comprise a first TVS diode, having a first breakdown voltage, and wherein the n-type inner region and the second surface region comprise a second TVS diode of opposite polarity to the first TVS diode, and having a second breakdown voltage, different from the first breakdown voltage. 
     
     
         11 . The method of  claim 10 , the first breakdown voltage being in a range of 15 V to 20 V, and the second breakdown voltage being in a range of 30 V to 35 V. 
     
     
         12 . The method of  claim 7 , the first dopant concentration comprising a range of 8E19/cm 3 , and the second dopant concentration comprising a range of 2E19/cm 3 . 
     
     
         13 . The method of  claim 7 , the first surface region comprising a first surface area, and the second surface region comprising a second surface area, the same as the first surface area. 
     
     
         14 . The method of  claim 7 , wherein the performing the first doping process comprises depositing a first dopant layer, having a first layer thickness, and performing a first drive in anneal, and
 wherein the performing the second doping process comprises depositing a second dopant layer, having a second layer thickness, and performing a second drive in anneal.   
     
     
         15 . The method of  claim 14 , wherein the performing the first layer thickness is different from the second layer thickness. 
     
     
         16 . The method of  claim 14 , wherein the first drive in anneal is different from the second drive in anneal. 
     
     
         17 . An asymmetric transient voltage suppression (TVS) device, comprising:
 a semiconductor substrate, the semiconductor substrate comprising inner region, the inner region having a first polarity;   a first surface region, disposed on a first surface of the semiconductor substrate, the first surface region comprising a second polarity; and   a second surface region, comprising the second polarity, and disposed on a second surface of the semiconductor substrate, opposite the first surface,   wherein the first surface region and the inner region define a first TVS diode having a first polarity, and a first breakdown voltage, and   wherein the second surface region and the inner region define a second TVS diode having a second polarity, and a second breakdown voltage, greater than the first breakdown voltage.   
     
     
         18 . The asymmetric TVS device of  claim 17 , comprising a mesa structure. 
     
     
         19 . The asymmetric TVS device of  claim 17 , comprising a planar structure.