Quasi-analog digital pulse-width modulation control

Abstract

A power supply for a smooth power output level transitioning includes an energy storage circuit for temporarily storing electric energy for driving a load, a semiconductor switch for pulse-width modulation (PWM) switching, and a digital PWM controller. The digital PWM controller generates a driving waveform to regulate on and off status of the semiconductor switch. The driving waveform toggles between PWM periods of a first type and PWM periods of a second type, and gradually adjusts a ratio of numbers of the PWM periods of the two types over time. The toggling driving waveform achieves one or more intermediate finer power output level that cannot be realized by a single type of PWM period with an intermediate duty cycle, due to the minimum item unit of the driving waveform limited by a clock rate of the digital PWM controller.

What is claimed is: 
     
         1 . An electrical apparatus comprising:
 an energy storage circuit configured to temporarily store electric energy for driving a load;   a semiconductor switch configured to turn on and off during pulse-width modulation (PWM) periods,
 wherein the semiconductor switch is electrically coupled between the energy storage circuit and an electric source; and 
   a digital controller configured to execute instructions for generating a driving waveform for the semiconductor switch,
 wherein the driving waveform toggles between PWM periods of a first type and PWM periods of a second type to transition from a first power output to a second power output, and 
 wherein transitioning from the first power output to the second power output requires that the driving waveform traverse at least one intermediate power output, each intermediate power output corresponding to a different ratio of PWM periods of the first type to PWM periods of the second type. 
   
     
     
         2 . The electrical apparatus of  claim 1 , wherein a dwell time at each intermediate power output is adjustable such that energy stored in the energy storage circuit stays beneath a predefined level. 
     
     
         3 . The electrical apparatus of  claim 1 , wherein a count of intermediate power outputs is adjustable such that each intermediate power output corresponds to a fixed percentage of a power differential between the first power output and the second power output. 
     
     
         4 . The electrical apparatus of  claim 1 ,
 wherein the first power output corresponds to the driving waveform being comprised solely of PWM periods of the first type, and   wherein the second power output corresponds to the driving waveform being comprised solely of PWM periods of the second type.   
     
     
         5 . The electrical apparatus of  claim 1 ,
 wherein the digital controller operates at a clock rate that determines a minimum time unit for the driving waveform, and   wherein the driving waveform remains constant during each minimum time unit.   
     
     
         6 . The electrical apparatus of  claim 5 , wherein a difference between on time of PWM periods of the first type and on time of PWM periods of the second type is an integer number of the minimum time unit. 
     
     
         7 . The electrical apparatus of  claim 5 , wherein a difference between off time of PWM periods of the first type and on time of PWM periods of the second type is an integer number of the minimum time unit. 
     
     
         8 . The electrical apparatus of  claim 1 ,
 wherein the at least one intermediate power output includes a third power output higher than the first power output and lower than the second power output, and   wherein the digital controller cannot produce the third power output by generating a driving waveform comprised of only PWM periods of a third type due to a minimum time unit determined by a clock rate at which the digital controller operates.   
     
     
         9 . The electrical apparatus of  claim 1 ,
 wherein a first duty cycle of PWM periods of the first type is different than a second duty cycle of PWM periods of the second type,   wherein a difference between switch-on time of PWM periods of the first type and switch-on time of PWM periods of the second type is a minimum time unit, and   wherein the digital controller cannot generate PWM periods having a duty cycle between the first and second duty cycles because the digital controller cannot change switch-on time by a fraction of the minimum time unit due to a clock rate limitation.   
     
     
         10 . The electrical apparatus of  claim 9 , wherein PWM periods of the first type and PWM periods of the second type have the same duration. 
     
     
         11 . A dimmer apparatus for a light source, the dimmer apparatus comprising:
 a receiver configured to receive a control signal for transitioning from a first power output to a second power output;   an energy storage circuit configured to temporarily store electric energy for driving the light source;   a semiconductor switch configured to turn on and off during pulse-width modulation (PWM) periods,
 wherein the semiconductor switch is electrically coupled between the energy storage circuit and an electric source; 
   a digital controller configured to execute instructions for generating a driving waveform for the semiconductor switch based on the control signal,
 wherein transitioning from the first power output to the second power output requires that the driving waveform traverse at least one intermediate power output, each intermediate power output corresponding to a different ratio of PWM periods of a first type to PWM periods of a second type. 
   
     
     
         12 . The dimmer apparatus of  claim 11 ,
 wherein the first power output corresponds to the driving waveform being comprised solely of PWM periods of the first type, and   wherein the second power output corresponds to the driving waveform being comprised solely of PWM periods of the second type.   
     
     
         13 . The dimmer apparatus of  claim 11 , wherein a dwell time at each intermediate power output is adjustable such that energy stored in the energy storage circuit stays beneath a predefined level. 
     
     
         14 . The dimmer apparatus of  claim 11 , wherein the driving waveform causes the power being applied to the light source to smoothly transition from the first power output to the second power output through a series of multiple intermediate power outputs such that the light source transitions from a first light intensity to a second light intensity through a series of multiple intermediate light intensities. 
     
     
         15 . The dimmer apparatus of  claim 14 , wherein the multiple intermediate light intensities cannot be discretely recognized by a human eye as the light source transitions from the first light intensity to the second light intensity. 
     
     
         16 . A method for smoothly transitioning between power outputs, the method comprising:
 receiving a control signal for transitioning from a first power output to a second power output;   determining that a digital controller cannot cause an intermediate power output between the first and second power outputs to be produced by generating a driving waveform that includes pulse-width modulation (PWM) periods of a single type;   generating a driving waveform that toggles between PWM periods of multiple types based on a single input signal; and   applying a series of power outputs produced by the driving waveform to a load over time,
 wherein the series of power outputs includes at least one intermediate power output through which power applied to the load transitions as the power transitions from the first power output to the second power output. 
   
     
     
         17 . The method of  claim 16 , wherein each intermediate power output corresponds to a different ratio of PWM periods of a first type to PWM periods of a second type. 
     
     
         18 . The method of  claim 16 , wherein a dwell time at each intermediate power output is adjustable such that energy stored in an energy storage circuit stays beneath a predefined level. 
     
     
         19 . The method of  claim 16 , further comprising:
 identifying PWM periods of a first type and PWM periods of a second type that, when combined, can produce the intermediate power output that cannot be produced by PWM periods of a single type,
 wherein PWM periods of the first and second types have different switch-on times, switch-off times, durations, minimum time units, or any combination thereof. 
   
     
     
         20 . The method of  claim 16 , wherein a dwell time at each intermediate power output is based on a count of intermediate power outputs.