Light emitting diodes and associated methods of manufacturing

Abstract

Light emitting diodes and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode (LED) includes a substrate, a semiconductor material carried by the substrate, and an active region proximate to the semiconductor material. The semiconductor material has a first surface proximate to the substrate and a second surface opposite the first surface. The second surface of the semiconductor material is generally non-planar, and the active region generally conforms to the non-planar second surface of the semiconductor material.

1 . A light emitting diode (LED) device, comprising:
 a substrate having a backside and a front side, wherein the front side is planar across the substrate;   a first semiconductor material carried by the substrate, the first semiconductor material having—
 a first major surface that is planar across the substrate, 
 a second major surface opposite the first major surface and farther from the substrate than the first major surface, 
 indentations tapering inwardly from the second major surface toward the substrate to define non-planar areas having an irregular pattern of peaks and valleys, wherein at least some of the indentations have different depths into the first semiconductor material than others such that the irregular patter of peaks and valleys have an irregular pattern of heights and depths relative to each other; and 
   an active region operably connected to the first semiconductor material via the second major surface.   
     
     
         2 . The LED device of  claim 1  wherein the active region (1) directly contacts the first semiconductor material at the second major surface and (2) conforms to the indentation. 
     
     
         3 . The LED device of  claim 2  wherein the active region is epitaxially aligned with the semiconductor material. 
     
     
         4 . The LED device of  claim 1  wherein:
 the individual indentations have a hexagonal base; and 
 the individual indentations taper inwardly from the hexagonal base toward the substrate. 
 
     
     
         5 . The LED device of  claim 1  wherein:
 the individual indentations have a plurality of sidewalls; and 
 individual sidewalls within the plurality of sidewalls are disposed along different respective crystal planes of the semiconductor material. 
 
     
     
         6 . The LED device of  claim 1  wherein the individual indentations have six sidewalls that converge at an apex. 
     
     
         7 . The LED device of  claim 1  wherein the indentations have a root-mean-square depth within a range from 0.05 micron to 3 microns. 
     
     
         8 . The LED device of  claim 1  wherein the planar region extends around the indentations at the second major surface. 
     
     
         9 . The LED device of  claim 1 , further comprising:
 a second semiconductor material, wherein the active region is disposed between the first and second semiconductor materials.   
     
     
         10 . The LED device of  claim 9  wherein:
 the first semiconductor material includes N-type gallium nitride (GaN); 
 the second semiconductor material includes P-type gallium nitride (GaN); and 
 the active region includes indium gallium nitride (InGaN). 
 
     
     
         11 . The LED device of  claim 1 , further comprising a buffer material between the substrate and the semiconductor material. 
     
     
         12 . The LED device of  claim 1 , further wherein the indentations are at different respective crystal dislocations within the semiconductor material. 
     
     
         13 . A method for making a light emitting diode (LED) device, comprising:
 providing a substrate having a backside and a front side, wherein the front side is planar across the substrate;   forming a first semiconductor material on the substrate, wherein the first semiconductor material has—
 a first major surface that is planar across the substrate, and 
 a second major surface opposite the first major surface and farther from the substrate than the first major surface; 
   forming indentations in the first semiconductor material, wherein the formed indentations taper inwardly from the second major surface toward the substrate to define non-planar areas having an irregular pattern of peaks and valleys, wherein at least some of the indentations have different depths into the first semiconductor material than others such that the irregular patter of peaks and valleys have an irregular pattern of heights and depths relative to each other; and   forming an active region on the first semiconductor material.   
     
     
         14 . The method of  claim 13 , further comprising forming a buffer material on the substrate before forming the first semiconductor material on the substrate. 
     
     
         15 . The method of  claim 13  wherein the formed indentations have a root-mean-square depth within a range from 0.05 micron to 3 microns. 
     
     
         16 . The method of  claim 13  wherein forming the active region includes epitaxially forming the active region. 
     
     
         17 . The method of  claim 13  wherein forming the active region includes forming the active region by metal organic chemical vapor deposition (MOCVD). 
     
     
         18 . The method of  claim 13  wherein forming the active region includes contacting the second major surface with phosphoric acid (H 3 PO 4 ). 
     
     
         19 . The method of  claim 13  wherein forming the active region includes contacting the second major surface with potassium hydroxide (KOH). 
     
     
         20 . The method of  claim 13  wherein:
 the first semiconductor material includes crystal dislocations at the second major surface; and 
 forming the indentations includes removing the first semiconductor material at the crystal dislocations. 
 
     
     
         21 . The method of  claim 13 , further comprising:
 forming a second semiconductor material, wherein the active region is disposed between the first and second semiconductor materials.   
     
     
         22 . The method of  claim 22  wherein:
 the first semiconductor material includes gallium nitride (GaN) with a crystal lattice structure adjacent to the crystal dislocations at the second major surface; 
 the second semiconductor material includes P-type gallium nitride (GaN); 
 the active region includes indium gallium nitride (InGaN); and 
 forming the indentations includes—
 removing gallium and nitrogen atoms from the semiconductor material at the crystal dislocations at a first rate, and 
 removing gallium and nitrogen atoms from the semiconductor material at the crystal lattice structure at a second rate less than the first rate.