Accelerator, method of operating the accelerator, and device including the accelerator

Abstract

A method of operating an accelerator includes receiving, from a central processing unit (CPU), commands for the accelerator and a peripheral device of the accelerator, processing the received commands according to a subject of performance of each of the commands, and transmitting a completion message indicating that performance of the commands is completed to the CPU after the performance of the commands is completed.

What is claimed is: 
     
         1 . A method of operating an accelerator, comprising:
 receiving, from a central processing unit (CPU), commands for the accelerator and a peripheral device of the accelerator;   processing the received commands according to a subject of performance of each of the commands; and   after performance of the commands is completed, transmitting a completion message indicating the completion of the performance of the commands to the CPU.   
     
     
         2 . The method of  claim 1 , wherein processing the commands comprises:
 in a case in which a subject to perform a target command, from among the commands, is the accelerator, performing the target command in the accelerator; and   in a case in which the subject to perform the target command is the peripheral device, transmitting the target command to the peripheral device.   
     
     
         3 . The method of  claim 2 , wherein, in the case in which the subject to perform the target command is the peripheral device, after the target command is transmitted from the accelerator to the peripheral device, the target command is performed in the peripheral device without intervention of the CPU. 
     
     
         4 . The method of  claim 2 , wherein, in the case in which the subject to perform the target command is the peripheral device, after the target command is performed in the peripheral device, a completion message indicating completion of the performance of the target command is transmitted from the peripheral device to the accelerator. 
     
     
         5 . The method of  claim 1 , wherein processing the commands comprises:
 after performance of a first command, from among the commands, is completed, processing a second command, which is a subsequent command of the first command, according to a corresponding subject of performance of the second command.   
     
     
         6 . The method of  claim 1 , wherein the accelerator is comprised in a device together with the CPU, and configured to perform a neural network-based inference among processes that are capable of being processed in the device. 
     
     
         7 . The method of  claim 1 , wherein at least one command for the accelerator, from among the commands, is a command for performing at least one neural network-based operation in the accelerator. 
     
     
         8 . The method of  claim 1 , wherein the commands received from the CPU are stored in a command queue comprised in the accelerator based on one or both of a dependency and a performance order. 
     
     
         9 . The method of  claim 1 , wherein processing the commands comprises:
 in a case in which a subject to perform a target command, from among the commands, is a peripheral device configured to communicate with another device, transmitting, to the peripheral device, a processing result of the accelerator together with the target command,   wherein the target command includes connection information associated with a connection with the other device.   
     
     
         10 . The method of  claim 1 , wherein processing the commands comprises:
 in a case in which a subject to perform a target command, from among the commands, is a storage device, transmitting, to the storage device, the target command including information indicating whether to read data from the storage device or write data in the storage device.   
     
     
         11 . The method of  claim 1 , wherein the accelerator, the CPU, and the peripheral device are configured to transmit or receive a data signal and/or a control signal through peripheral component interconnect express (PCIe) communication in a same device. 
     
     
         12 . A non-transitory computer-readable storage medium storing commands that, when executed by a processor, cause the processor to perform the method of  claim 1 . 
     
     
         13 . An accelerator comprising:
 a core controller configured to transmit, to an accelerator controller or a peripheral device controller, a target command to be performed, from among commands received from a central processing unit (CPU) and stored in a command queue according to a subject of performance of each command;   the accelerator controller configured to receive, from the core controller, the target command in a case in which the accelerator is a subject to perform the target command, and perform the received target command; and   the peripheral device controller configured to receive, from the core controller, the target command in a case in which a peripheral device is the subject to perform the target command, and transmit the received target command to the peripheral device,   wherein, after performance of the commands stored in the command queue is completed, the core controller is configured to transmit, to the CPU, a completion message indicating completion of the performance of the commands.   
     
     
         14 . The accelerator of  claim 13 , wherein, after performance of a first command, from among the commands, is completed, the core controller is configured to transmit, to the accelerator controller or the peripheral device controller, a second command, which is a subsequent command of the first command according to a corresponding subject of performance of the second command. 
     
     
         15 . The accelerator of  claim 13 , wherein the accelerator is comprised in a device together with the CPU, and is configured to perform a neural network-based inference among processes that are capable of being processed in the device. 
     
     
         16 . The accelerator of  claim 13 , wherein the command queue is comprised in the accelerator and the commands received from the CPU are stored in the command queue based on one or both of a dependency and a performance order. 
     
     
         17 . The accelerator of  claim 13 , wherein the accelerator, the CPU, and the peripheral device are configured to transmit or receive a data signal and/or a control signal through peripheral component interconnect express (PCIe) communication in a same device. 
     
     
         18 . A device comprising:
 a central processing unit (CPU) configured to transmit, to an accelerator, commands for the accelerator and a peripheral device;   the accelerator configured to perform a target command, from among the commands, in a case in which the target command is to be performed by the accelerator, and transmit, to the peripheral device, the target command in a case in which the target command is to be performed by the peripheral device; and   the peripheral device configured to perform the target command received from the accelerator in the case in which the target command is to be performed by the peripheral device,   wherein, after performance of the commands is completed, the accelerator is configured to transmit, to the CPU, a completion message indicating completion of the performance of the commands.   
     
     
         19 . The device of  claim 18 , wherein, in the case in which the target command is to be performed by the peripheral device, after the target command is transmitted from the accelerator to the peripheral device, the target command is performed in the peripheral device without intervention of the CPU. 
     
     
         20 . An accelerator, comprising:
 one or more processors configured to:
 receive, from a central processing unit (CPU), one or more commands to be processed; 
 determine, for each of the commands, whether the respective command is to be processed by the one or more processors or to be processed by a peripheral device; 
 in a case in which it is determined that the respective command is to be processed by the one or more processors, process the respective command; 
 in a case in which it is determined that the respective command is to be processed by the peripheral device, transmit the command to the peripheral device; and 
 transmit a completion message to the CPU only after it is confirmed that all of the commands have been processed. 
   
     
     
         21 . The accelerator according to  claim 20 , wherein the one or more processors are configured to determine, for each of the commands, whether the respective command is to be processed by the one or more processors or to be processed by the peripheral device based on whether the respective command requires performance of a neural network-based inference or calculation of a gradient for neural network learning. 
     
     
         22 . The accelerator according to  claim 20 , wherein the one or more processors are configured to transmit, in the case in which it is determined that the respective command is to be processed by the peripheral device, a processing result of the one or more processors to the peripheral device, in a case in which it is determined that the processing result is needed for the peripheral device to perform the respective command. 
     
     
         23 . The accelerator according to  claim 20 , wherein the one or more processors are configured to transmit the completion message to the CPU after receiving a command completion message from the peripheral device indicating that all of the commands to be processed by the peripheral device have been processed by the peripheral device.