Performing Rounding Operations Responsive To An Instruction

Abstract

In one embodiment, the present invention includes a method for receiving a rounding instruction and an immediate value in a processor, determining if a rounding mode override indicator of the immediate value is active, and if so executing a rounding operation on a source operand in a floating point unit of the processor responsive to the rounding instruction and according to a rounding mode set forth in the immediate operand. Other embodiments are described and claimed.

1 . (canceled) 
     
     
         2 : A processor comprising:
 a plurality of cores, at least one of the plurality of cores comprising:
 a plurality of registers including a first register and a second register, wherein the first register and the second register comprise extended registers; 
 a control register having a first field to indicate a current floating point round mode, and a second field to indicate whether denormals are to be converted to zero; 
 a status register having a third field to store a value, the value to indicate whether an inexact exception has occurred, wherein the status register is separate from the control register; 
 a control unit to receive a user-level round instruction and to decode fields of the user-level round instruction, the user-level round instruction to only specify a round operation and to identify the first register, which is to store a source operand with a plurality of packed double precision floating point values, the user-level round instruction to indicate that the current floating point round mode is to be used, and the user-level round instruction to indicate to suppress a change in the value of the third field of the status register; and 
 an execution unit coupled to the control unit, in response to the user-level round instruction, to:
 convert a denormal of the source operand to zero when the second field indicates that the denormals are to be converted to zero; 
 perform the round operation according to the current floating point round mode, to generate integral valued packed double precision floating point values; and 
 store the integral valued packed double precision floating point values in the second register. 
 
   
     
     
         3 : The processor of  claim 2 , wherein a bit of the user-level round instruction is to have a value of one when the user-level round instruction is to indicate to suppress the change in the value of the third field of the status register. 
     
     
         4 : The processor of  claim 2 , wherein the current floating point round mode is to be any one of:
 round towards negative infinity;   round towards positive infinity;   round to zero; and   round to nearest even.   
     
     
         5 : The processor of  claim 2 , wherein the user-level round instruction is included in an instruction set architecture (ISA) with a second round instruction to indicate a packed data register to store a scalar value, and wherein the second round instruction is to cause the processor to perform a round operation on the scalar value to generate an integral valued floating point value. 
     
     
         6 : The processor of  claim 2 , wherein the user-level round instruction is included in an instruction set architecture (ISA) with another round instruction to indicate another register to store a scalar value, and wherein the another round instruction is to cause the processor to perform a round operation on the scalar value to generate an integer value. 
     
     
         7 : A system comprising:
 a memory controller; and   a core coupled to the memory controller, the core comprising:
 a plurality of registers including a first register and a second register, wherein the first register and the second register comprise extended registers; 
 a control register having a first field to indicate a current floating point round mode, and a second field to indicate whether denormals are to be converted to zero; 
 a status register having a third field to store a value, the value to indicate whether an inexact exception has occurred, wherein the status register is separate from the control register; 
 a control unit to receive a round instruction and to decode fields of the round instruction, the round instruction only to specify a round operation and to identify the first register, which is to store a source operand with a plurality of packed double precision floating point values, the round instruction to indicate that the current floating point round mode is to be used, and the round instruction to indicate to suppress a change in the value of the third field of the status register; and 
 an execution unit coupled to the control unit, in response to the round instruction, to:
 convert a denormal of the source operand to zero when the second field indicates that the denormals are to be converted to zero; 
 perform the round operation according to the current floating point round mode, to generate integral valued packed double precision floating point values; and 
 store the integral valued packed double precision floating point values in the second register. 
 
   
     
     
         8 : The system of  claim 7 , wherein a bit of the round instruction is to have a value of one when the round instruction is to indicate to suppress the change in the value of the third field of the status register. 
     
     
         9 : The system of  claim 7 , wherein the current floating point round mode is to be any one of:
 round towards negative infinity;   round towards positive infinity;   round to zero; and   round to nearest even.   
     
     
         10 : The system of  claim 7 , wherein the round instruction is included in an instruction set architecture (ISA) with a second round instruction to indicate a packed data register to store a scalar value, and wherein the second round instruction is to cause the processor to perform a round operation on the scalar value to generate an integral valued floating point value. 
     
     
         11 : The system of  claim 7 , wherein the round instruction is included in an instruction set architecture (ISA) with another round instruction to indicate another register to store a scalar value, and wherein the second round instruction is to cause the processor to perform a round operation on the scalar value to generate an integer value. 
     
     
         12 : The system of  claim 7 , further comprising a communication device coupled to the core. 
     
     
         13 : The system of  claim 7 , further comprising an I/O device coupled to the core. 
     
     
         14 : The system of  claim 7 , further comprising a graphics engine coupled to the core. 
     
     
         15 : The system of  claim 7 , further comprising a Peripheral Component Interconnect (PCI) Express bus coupled to the core. 
     
     
         16 : The system of  claim 7 , further comprising audio I/O coupled to the core. 
     
     
         17 : A system comprising:
 a first processor;   a second processor coupled to the first processor via a point-to-point interconnect, the second processor comprising:
 a plurality of registers including a first register and a second register; 
 a control register having a first field to indicate a current floating point round mode, and a second field to indicate whether denormals are to be converted to zero; 
 a status register having a third field to store a value, the value to indicate whether an inexact exception has occurred, wherein the status register is separate from the control register; 
 a control unit to receive a round instruction and to decode fields of the round instruction, the round instruction only to specify a round operation and to identify the first register, which is to store a source operand with a plurality of packed double precision floating point values, the round instruction to indicate that the current floating point round mode is to be used and to indicate to suppress a change in the value of the third field of the status register; and 
 an execution unit coupled to the control unit, in response to the round instruction, to:
 convert a denormal of the source operand to zero when the second field indicates that the denormals are to be converted to zero; 
 perform the round operation according to the current floating point round mode, to generate integral valued packed double precision floating point values; and 
 store the integral valued packed double precision floating point values in the second register; 
 
   a first memory coupled to the first processor; and   a second memory coupled to the second processor.   
     
     
         18 : The system of  claim 17 , wherein a bit of the round instruction is to have a value of one when the round instruction is to indicate to suppress the change in the value of the third field of the status register. 
     
     
         19 : The system of  claim 17 , wherein the current floating point round mode is to be any one of:
 round towards negative infinity;   round towards positive infinity;   round to zero; and   round to nearest even.   
     
     
         20 : The system of  claim 17 , wherein the round instruction is included in an instruction set architecture (ISA) with a second round instruction to indicate a packed data register to store a scalar value, and wherein the second round instruction is to cause the first processor to perform a round operation on the scalar value to generate an integral valued floating point value. 
     
     
         21 : The system of  claim 17 , further comprising a communication device coupled to the first processor.