Systems and methods for input/output computing resource control

Abstract

Disclosed herein are systems and methods for isolating input/output computing resources. In some embodiments, a host device may include a processor and logic coupled with the processor, to identify a tag identifier (Tag ID) for a process or container of the host device. The Tag ID may identify a queue pair of a hardware device of the host device for an outbound transaction from the processor to the hardware device, to be conducted by the process or container. Logic may further map the Tag ID to a Process Address Space Identifier (PASID) associated with an inbound transaction from the hardware device to the processor that used the identified queue pair. The process or container may use the PASID to conduct the outbound transaction via the identified queue pair. Other embodiments may be disclosed and/or claimed.

What is claimed is: 
     
         1 . A method comprising:
 receiving, at a device, a request to access a register from a Peripheral Component Interconnect Express (PCIe) consistent communication, wherein the PCIe consistent communication conveys a process identifier, wherein the process identifier is associated with at least one queue pair, and wherein registers of the hardware device are allocated to particular process identifiers to provide register isolation among processes and   selectively providing, at the device, read or write access to the register associated with the process identifier.   
     
     
         2 . The method of  claim 1 , comprising:
 associating, using a device driver, the process identifier with the at least one queue pair.   
     
     
         3 . The method of  claim 1 , wherein receiving, at a device, a request to access a register from a PCIe consistent communication comprises:
 receiving, from a root complex, the process identifier using the PCIe consistent communication, wherein the root complex receives the process identifier using a memory-mapped I/O (MMIO) or port-mapped I/O (PIO).   
     
     
         4 . The method of  claim 1 , wherein selectively providing, at the device, read or write access to the register associated with the process identifier comprises:
 determining, at the device, permission to access the register based on the process identifier received in the PCIe consistent communication and   permitting or denying access, at the device, to the register based on the determined permission to access the register.   
     
     
         5 . The method of  claim 1 , wherein the process identifier comprises a namespace ID or Tag ID. 
     
     
         6 . The method of  claim 1 , wherein a process comprises a container or virtual execution environment and the process provides the request to access a register. 
     
     
         7 . The method of  claim 1 , wherein the PCIe consistent communication conveys the process identifier in a PASID TLP prefix. 
     
     
         8 . The method of  claim 1 , wherein the at least one queue pair comprises a receive queue and a transmit queue in memory accessible to the device. 
     
     
         9 . The method of  claim 1 , wherein the device comprises a network interface controller (NIC). 
     
     
         10 . An apparatus, comprising:
 a hardware device comprising:
 circuitry to receive a request to access a register from a Peripheral Component Interconnect Express (PCIe) consistent communication, wherein the PCIe consistent communication is to convey a process identifier, wherein the process identifier is associated with at least one queue pair, and wherein registers of the hardware device are allocated to particular process identifiers to provide register isolation among processes and 
 circuitry to selectively provide read or write access to the register associated with the process identifier. 
   
     
     
         11 . The apparatus of  claim 10 , wherein a privileged agent is to associate the process identifier with the at least one queue pair. 
     
     
         12 . The apparatus of  claim 10 , wherein the receive a request to access a register from a PCIe consistent communication comprises:
 receive, from a system agent, the process identifier using the PCIe consistent communication, wherein the system agent receives the process identifier using a memory-mapped I/O (MMIO) or port-mapped I/O (PIO).   
     
     
         13 . The apparatus of  claim 10 , wherein the circuitry to selectively provide read or write access to the register associated with the process identifier is to:
 determine permission to access the register based on the process identifier received in the PCIe consistent communication and   permit or deny access to the register based on the determined permission to access the register.   
     
     
         14 . The apparatus of  claim 10 , wherein the process identifier comprises a namespace ID or Tag ID. 
     
     
         15 . The apparatus of  claim 10 , wherein a process comprises a container or virtual execution environment and wherein the process is provide the request to access a register. 
     
     
         16 . The apparatus of  claim 10 , wherein the PCIe consistent communication is to provide the process identifier in a PASID TLP prefix. 
     
     
         17 . The apparatus of  claim 10 , wherein the at least one queue pair comprises a receive queue and a transmit queue in memory accessible to the device. 
     
     
         18 . The apparatus of  claim 10 , wherein the device comprises a network interface controller (NIC). 
     
     
         19 . The apparatus of  claim 10 , comprising:
 a central processing unit (CPU) comprising at least one core, wherein a core is to execute a process, wherein the process is to issue the request to access a register and wherein the CPU is communicatively coupled to the hardware device.   
     
     
         20 . The apparatus of  claim 19 , comprising:
 a system agent to communicatively couple the CPU with the hardware device.