Low Resistance Vertical Cavity Light Source with PNPN Blocking
Abstract
A semiconductor vertical light source includes upper and lower mirrors with an active region in between, an inner mode confinement region, and an outer current blocking region that includes a common epitaxial layer including an epitaxially regrown interface between the active region and upper mirror. A conducting channel including acceptors is in the inner mode confinement region. The current blocking region includes a first impurity doped region with donors between the epitaxially regrown interface and active region, and a second impurity doped region with acceptors between the first doped region and lower mirror. The outer current blocking region provides a PNPN current blocking region that includes the upper mirror or a p-type layer, first doped region, second doped region, and lower mirror or an n-type layer. The first and second impurity doped region force current flow into the conducting channel during normal operation of the light source.
Claims
exact text as granted — not AI-modified1 . A semiconductor vertical resonant cavity light source (vertical light source), comprising:
an active region within said vertical resonant cavity for light generation; at least one upper p-region above said active region; at least one lower n-region below said active region; an outer current blocking region and an inner mode confinement region within said outer current blocking region; said outer current blocking region comprising a common epitaxial layer that includes an epitaxially regrown interface extending over said inner mode confinement region and over said outer current blocking region which is between said active region and said upper mirror; and and wherein said outer current blocking region provides a PNPN current blocking region comprising said upper p-region; a first impurity doped region comprising donor impurities between said epitaxially regrown interface and said active region; and a second impurity doped region comprising acceptor impurities between said first impurity doped region and said lower n-region.
2 . The light source of claim 1 , further comprising an upper mirror comprised of one or more regions comprising p-type doping.
3 . The light source of claim 1 , further comprising a lower mirror comprised of one or more regions comprising n-type doping.
4 . The vertical cavity light source of claim 1 , wherein said light source comprises a vertical-cavity surface-emitting laser (VCSEL).
5 . A semiconductor vertical resonant cavity light source, comprising:
an upper p-region and a lower n-region; an active region for light generation between said upper p-region and said lower n-region; said light source including an inner mode confinement region and an outer current blocking region; said outer current blocking region comprising a common epitaxial layer that includes an epitaxially regrown interface extending over said inner mode confinement region and over said outer current blocking region which is between said active region and said upper p-region; wherein said outer current blocking region provides a PNPN current blocking region comprising said upper p-region; a first impurity doped region comprising donor impurities between said epitaxially regrown interface and said active region; and a second impurity doped region comprising acceptor impurities between said first impurity doped region and said lower n-region.
6 . The light source of claim 1 , further comprising an upper mirror comprised of one or more regions comprising p-type doping.
7 . The light source of claim 1 , further comprising a lower mirror comprised of one or more regions comprising n-type doping.
8 . The light source of claim 5 , wherein said light source comprises a vertical-cavity surface-emitting laser (VCSEL).
9 . A method for forming a semiconductor vertical cavity light source (vertical light source), comprising:
forming a partial vertical light source, comprising forming:
a lower n-type region;
an active region within said vertical resonant cavity for light generation;
at least one epitaxial common layer over said cavity spacer region;
patterning at least one said epitaxial common layer to define at least one region intended to form mode confining regions such that said common layer remains covering at least within said region intended to form said mode confining regions;
placing said patterned partial vertical cavity light source into an epitaxial growth system, and then: epitaxial growing to deposit at least one epitaxial upper p-type region; wherein said outer current blocking region provides a PNPN current blocking region comprising said upper p-region; a first impurity doped region comprising donor impurities between said epitaxially regrown interface and said active region; and a second impurity doped region comprising acceptor impurities between said first impurity doped region and said lower n-region.Join the waitlist — get patent alerts
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