US2021224206A1PendingUtilityA1

Hub circuit for a dimm having multiple components that communicate with a host

Assignee: INTEL CORPPriority: Mar 16, 2018Filed: Apr 5, 2021Published: Jul 22, 2021
Est. expiryMar 16, 2038(~11.6 yrs left)· nominal 20-yr term from priority
G06F 13/409G11C 7/22G06F 2213/3808G06F 13/1684G06F 13/4234G06F 13/4022G06F 1/185G11C 5/04G11C 7/1003G06F 13/385G11C 5/02
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Claims

Abstract

An apparatus is described. The apparatus includes a DIMM hub circuit. The DIMM hub circuit includes first bus interface circuitry, control circuitry and second bus interface circuitry. The first bus interface circuitry is to receive header information and payload information from a host. The control circuitry is to process the header information and recognize that the payload is to be passed to a target component that is coupled to the DIMM hub circuit through a second bus that is a same type of bus as the first bus. The second bus interface circuitry to send the payload information over the second bus to the target component, wherein, the payload information is to include embedded header information to be processed by the target component.

Claims

exact text as granted — not AI-modified
1 . A system comprising:
 a host side bus to receive and transfer a communication comprising a 4-bit local bus device identifier, a 3-bit HID code, and payload, wherein
 the 4-bit local bus device identifier is to identify that the communication is to be provided to a component connected to a local bus, 
 the 3-bit HID code is to identify a selected hub device among hubs connected to the host side bus; and 
   hub circuitry to:
 process the 4-bit local bus device identifier and process the 3-bit HID code to determine whether the payload is to be transferred to a component through the hub circuitry and through a local bus, wherein based on a determination that the payload is to be transferred to the component through the selected hub device and through the local bus, the hub circuitry is to send the payload over the local bus to the component. 
   
     
     
         2 . The system of  claim 1 , wherein the component comprises a dual in-line memory module (DIMM) system. 
     
     
         3 . The system of  claim 1 , wherein the host side bus and the local bus are Mobile Industry Processor Interface (MIPI) I3C standard compatible buses. 
     
     
         4 . The system of  claim 1 , wherein the hub circuitry is to:
 store and forward copies of the payload to multiple components connected to the local bus.   
     
     
         5 . A method comprising:
 receiving, at a host side bus, a communication comprising a 4-bit local bus device identifier, a 3-bit HID code, and payload, wherein
 the 4-bit local bus device identifier is to identify that the communication is to be provided to a component connected to a local bus, 
 the 3-bit HID code is to identify a selected hub device among hubs connected to the host side bus; 
   determining, at hub circuitry, whether the payload is to be transferred to a component through the hub circuitry and through a local bus based on the 4-bit local bus device identifier and the 3-bit HID code; and   sending, by the hub circuitry, the payload over the local bus to the component based on a determination that the payload is to be transferred to the component through the selected hub device and through the local bus.   
     
     
         6 . The method of  claim 5 , wherein the component comprises a dual in-line memory module (DIMM) system. 
     
     
         7 . The method of  claim 5 , wherein the host side bus and the local bus are Mobile Industry Processor Interface (MIPI) I3C standard compatible buses. 
     
     
         8 . The method of  claim 5 , comprising:
 storing and forwarding copies of the payload, by the hub circuitry, to multiple components connected to the local bus.

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