System for accurate multiple level gain cells

Abstract

A dynamic gain cell memory cell capable of storing multiple values is described herein. In one example, a memory cell may include an input, such as a first transistor. The memory cell may further include a capacitive element coupled to the input, where the capacitive element stores one or more values corresponding to one of multiple voltage levels. A sense transistor configured to operate in source-follower mode may be coupled to the capacitive element, where the charge on the capacitive element controls operation of the sense transistor, such as through a gate of the sense transistor. The memory cell may further include an output connected to the drain of the sense transistor, where current flows through the transistor when the output is activated to access the one or more values stored in capacitive element.

What is claimed is: 
     
         1 . A dynamic memory cell array comprising:
 a plurality of memory cells, wherein the plurality of memory cells are connected by a read line and a write line, wherein each memory cell comprises a multi-level dynamic access memory cell that stores one or more values;   at least one reference cell, wherein the reference cell stores and outputs a reference value; and   a control circuit configured to modify one or more threshold values corresponding to at least one of the plurality of memory cells based on the reference value, wherein the one or more threshold values are used to compared to the one or more values stored in the corresponding at least one of the plurality of memory cells to determine data stored in the corresponding at least one of the plurality of memory cells.   
     
     
         2 . The dynamic memory cell array of  claim 1 , wherein each memory cell comprises:
 a capacitive element coupled to the input, wherein the capacitive element stores the one or more values corresponding to one of multiple voltage levels;   a transistor coupled to the capacitive element, wherein the charge on the capacitive element controls operation of the transistor via a gate of the transistor, wherein the transistor operates in source-follower mode; and   an output connected to the drain of the transistor, wherein current flows through the transistor when the output is activated to access the one or more values stored in capacitive element.   
     
     
         3 . The dynamic memory cell array of  claim 1 , wherein the reference value is set in the at least one reference cell contemporaneously with the one or more values being stored in at least a subset of the plurality of memory cells, wherein the reference value is associated with the subset of the plurality of memory cells and wherein modifying the one or more threshold values based on the reference value further comprises changing the one or more threshold values to match the reference value after a time period. 
     
     
         4 . The dynamic memory cell array of  claim 1 , wherein the at least one reference cell comprises a plurality of reference cells, each storing a reference value, disposed at least substantially uniformly throughout the dynamic memory cell array; and wherein
 the control circuit is further configured to modify the one or more corresponding threshold values based on the reference values obtained from reference cells proximate to the one of the plurality of memory cells.   
     
     
         5 . A dynamic memory cell array comprising:
 a plurality of memory cells, wherein the plurality of memory cells are connected by a read line and a write line and have at least one input, wherein a first memory cell of the plurality of memory cells comprises a dynamic access memory cell that stores one value of at least three different values;   at least one reference cell, wherein the reference cell stores a reference value; and   a control circuit configured to:
 determine at least one threshold value corresponding to the first memory cell based on the reference value; and 
 compare the one value stored in the first memory cell with the at least one threshold value to determine data stored in the first memory cell. 
   
     
     
         6 . The dynamic memory cell array of  claim 5 , wherein at least the first memory cell comprises:
 a capacitive element coupled to the input, wherein the capacitive element stores one of a plurality of voltage levels representing the one value.   
     
     
         7 . The dynamic memory cell array of  claim 6 , wherein at least the first memory cell further comprises:
 a transistor coupled to the capacitive element, wherein the charge on the capacitive element controls operation of the transistor via a gate of the transistor, wherein the transistor operates in source-follower mode; and   an output connected to the drain of the transistor, wherein current flows through the transistor when the output is activated to access the one or more values stored in capacitive element.   
     
     
         8 . The dynamic memory cell array of  claim 5 , wherein at least the first memory cell comprises:
 a transistor coupled to the capacitive element, wherein the charge on the capacitive element controls operation of the transistor via a gate of the transistor, wherein the transistor operates in source-follower mode.   
     
     
         9 . The dynamic memory cell array of  claim 5 , wherein the reference value is set in the reference cell contemporaneously with the one value being stored in the first memory cell, and wherein modifying the at least one threshold value based on the reference value further comprises changing the at least one threshold value by a first value to substantially match a change in the reference value after a time period. 
     
     
         10 . The dynamic memory cell array of  claim 1 , wherein the at least one reference cell comprises a plurality of reference cells, each storing a reference value, disposed at throughout the dynamic memory cell array; and wherein
 the control circuit is further configured to modify the one or more corresponding threshold values based on the reference values obtained from reference cells proximate to the one of the plurality of memory cells.   
     
     
         11 . The dynamic memory cell array of  claim 5 , wherein the control circuit is further configured to refresh the one value stored in the first memory cell. 
     
     
         12 . The dynamic memory cell array of  claim 11 , wherein refreshing the one value stored in the first memory cell is performed responsive to the reference value going below a threshold value. 
     
     
         13 . The dynamic memory cell array of  claim 5 , further comprising a second memory cell storing a second reference value, wherein the reference value and the second reference value each correspond to at least one of the at least three different values stored by the first memory cell. 
     
     
         14 . The dynamic memory cell array of  claim 5 , further comprising a feedback mechanism configured to:
 capture the one value as the one value is stored in the first memory cell; and   adjust the one value such that the one value stored in the first memory cell converges to cause a resultant output to match one or more nominal values that represent the data stored by the first memory cell.   
     
     
         15 . A dynamic memory system comprising:
 a plurality of memory cells, wherein a first memory cell of the plurality of memory cells comprises:
 a capacitive element that stores a first voltage level of a plurality of voltage levels, the first voltage level corresponding to a first value of at least three different values; and 
 a transistor coupled to the capacitive element, wherein the charge on the capacitive element controls operation of the transistor, wherein the transistor operates in source-follower mode; 
   at least one reference cell, wherein the reference cell stores a reference value; and   a control circuit configured to:
 modify at least one threshold value corresponding to the first memory cell based on a change in the reference value over a time period to generate at least one modified threshold value; and 
 compare the one value stored in the first memory cell with the at least one modified threshold value to determine data stored in the first memory cell. 
   
     
     
         16 . The dynamic memory system of  claim 15 , wherein at least the first memory cell further comprises:
 an output connected to the drain of the transistor, wherein current flows through the transistor when the output is activated to access the first value stored in capacitive element.   
     
     
         17 . The dynamic memory system of  claim 15 , wherein the reference value is set in the reference cell contemporaneously with the one value being stored in the first memory cell. 
     
     
         18 . The dynamic memory system of  claim 15 , wherein the at least one reference cell comprises a plurality of reference cells, each storing a reference value, located throughout the dynamic memory system; and wherein
 the control circuit is further configured to modify the at least one corresponding threshold value based on the reference values obtained from reference cells proximate to the first memory cell.   
     
     
         19 . The dynamic memory system of  claim 15 , wherein the control circuit is further configured to refresh the one value stored in the first memory cell based on at least one of an elapsed period of time or responsive to the reference value going below a threshold value. 
     
     
         20 . The dynamic memory system of  claim 15 , wherein in the reference value corresponds to the first value of the at least three different values, the system further comprising:
 a second memory cell storing a second reference value, the second reference value corresponding to a second value of the at least three different values; and   a third memory cell storing a third reference value, the third reference value corresponding to a third value of the at least three different values.