US2021232426A1PendingUtilityA1

Apparatus, method, and system for ensuring quality of service for multi-threading processor cores

Assignee: INTEL CORPPriority: Mar 29, 2019Filed: Nov 10, 2020Published: Jul 29, 2021
Est. expiryMar 29, 2039(~12.7 yrs left)· nominal 20-yr term from priority
G06F 9/3851G06F 9/3854G06F 9/38G06F 2209/5021G06F 9/544G06F 2209/507G06F 9/382G06F 9/5038G06F 3/064G06F 9/5061G06F 9/4881H04L 41/5025G06F 9/4818G06F 9/30101G06F 9/5011G06F 2212/1024G06F 2209/5018
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Claims

Abstract

A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Claims

exact text as granted — not AI-modified
1 - 25 . (canceled) 
     
     
         26 . A processor comprising:
 a plurality of registers, each register to store a service level for one of a plurality of threads to be executed;   a priority controller to determine a priority level for each of the plurality of threads based on the service levels stored in the registers and to generate a priority vector comprising the determined priority levels for each of the plurality of threads; and   one or more pipelines each comprising a plurality of pipeline stages to execute the plurality of threads, wherein each pipeline stage is to prioritize execution of the threads based on the priority level of each thread in the priority vector, wherein a first thread is prioritized for execution over a second thread when the first thread is of a higher priority level than the second thread.   
     
     
         27 . The processor of  claim 26 , wherein each service level specifies, or is mapped to, a priority level. 
     
     
         28 . The processor of  claim 26 , wherein at each pipeline stage, the first thread is assigned more execution cycles than the second thread. 
     
     
         29 . The processor of  claim 27 , wherein during execution cycles assigned to the first thread, available tasks from the first thread will be selected for execution before tasks from other threads are selected. 
     
     
         30 . The processor of  claim 29 , wherein during execution cycles assigned to the first thread, tasks from other threads will be selected for execution when there are no available tasks for execution from the first thread. 
     
     
         31 . The processor of  claim 26 , wherein the plurality of pipeline stages comprises an instruction decode stage, a branch prediction stage, an execution stage, and/or a retirement stage. 
     
     
         32 . The processor of  claim 26 , further comprising a resource controller to control assignment of a shared resource to the plurality of threads based on the priority level of each thread in the priority vector, wherein each of the plurality of threads is initially assigned one unit of the shared resource and any remaining units of the shared resource is assigned amongst threads of high priority level. 
     
     
         33 . The processor of  claim 32 , wherein threads of low priority level are not assigned any units of the shared resource besides the one unit that was initially assigned. 
     
     
         34 . A method comprising:
 storing, in each of a plurality of registers, a service level for one of a plurality of threads to be executed;   determining a priority level for each of the plurality of threads based on the service levels stored in the plurality of registers;   generating a priority vector comprising the determined priority levels for each of the plurality of threads; and   prioritizing execution of the plurality of threads at each of a plurality of pipeline stages of a processing pipeline based on the priority level of each thread in the priority vector, wherein a first thread is prioritized for execution over a second thread when the first thread is of a higher priority level than the second thread.   
     
     
         35 . The method of  claim 34 , wherein each service level specifies, or is mapped to, a priority level. 
     
     
         36 . The method of  claim 34 , further comprising assigning, at each pipeline stage, more execution cycles to the first thread than to the second thread. 
     
     
         37 . The method of  claim 35 , further comprising, during execution cycles assigned to the first thread, selecting available tasks from the first thread for execution before selecting tasks from other threads. 
     
     
         38 . The method of  claim 37 , further comprising, during execution cycles assigned to the first thread, selecting tasks from other threads for execution when there are no available tasks for execution from the first thread. 
     
     
         39 . The method of  claim 34 , wherein the plurality of pipeline stages comprises an instruction decode stage, a branch prediction stage, an execution stage, and/or an retirement stage. 
     
     
         40 . The method of  claim 34 , further comprising controlling assignment of a shared resource to the plurality of threads based on the priority level of each thread in the priority vector, wherein each of the plurality of threads is initially assigned one unit of the shared resource and any remaining units of the shared resource is assigned amongst threads of high priority level. 
     
     
         41 . The method of  claim 40 , wherein threads of low priority level are not assigned any units of the shared resource besides the one unit that was initially assigned. 
     
     
         42 . A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform operations of:
 storing, in each of a plurality of registers, a service level for one of a plurality of threads to be executed;   determining a priority level for each of the plurality of threads based on the service levels stored in the plurality of registers;   generating a priority vector comprising the determined priority levels for each of the plurality of threads; and   prioritizing execution of the plurality of threads at each of a plurality of pipeline stages of a processing pipeline based on the priority level of each thread in the priority vector, wherein a first thread is prioritized for execution over a second thread when the first thread is of a higher priority level than the second thread.   
     
     
         43 . The non-transitory machine-readable medium of  claim 42 , wherein each service level specifies, or is mapped to, a priority level. 
     
     
         44 . The non-transitory machine-readable medium of  claim 42 , wherein the operations further comprise assigning, at each pipeline stage, more execution cycles to the first thread than to the second thread. 
     
     
         45 . The non-transitory machine-readable medium of  claim 43 , wherein the operations further comprise, during execution cycles assigned to the first thread, selecting available tasks from the first thread for execution before selecting tasks from other threads. 
     
     
         46 . The non-transitory machine-readable medium of  claim 45 , wherein the operations further comprise, during execution cycles assigned to the first thread, selecting tasks from other threads for execution when there are no available tasks for execution from the first thread. 
     
     
         47 . The non-transitory machine-readable medium of  claim 42 , wherein the plurality of pipeline stages comprises an instruction decode stage, a branch prediction stage, an execution stage, and/or an retirement stage. 
     
     
         48 . The non-transitory machine-readable medium of  claim 42 , wherein the operations further comprise controlling assignment of a shared resource to the plurality of threads based on the priority level of each thread in the priority vector, wherein each of the plurality of threads is initially assigned one unit of the shared resource and any remaining units of the shared resource is assigned amongst threads of high priority level. 
     
     
         49 . The non-transitory machine-readable medium of  claim 48 , wherein threads of low priority level are not assigned any units of the shared resource besides the one unit that was initially assigned.

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