Integrated Transistors and Methods of Forming Integrated Transistors

Abstract

Some embodiments include an integrated device having a first transistor gate over a first region of a semiconductor base, and having a second transistor gate over a second region of the semiconductor base. First sidewall spacers are along sidewalls of the first transistor gate. The first sidewall spacers include SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry. The first sidewall spacers have a first thickness. Second sidewall spacers are along sidewalls of the second transistor gate. The second sidewall spacers have a second thickness which is less than the first thickness. First source/drain regions are within the semiconductor base and are operatively proximate the first transistor gate. Second source/drain regions are within the semiconductor base and are operatively proximate the second transistor gate. Some embodiments include methods of forming integrated devices.

I/we claim,: 
     
         1 . An integrated device, comprising:
 a transistor gate over a semiconductor base;   sidewall spacers along sidewalls of the transistor gate; the sidewall spacers comprising SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry; and   source/drain regions within the semiconductor base and operatively proximate the first transistor gate.   
     
     
         2 . The integrated device of  claim 1  wherein the sidewall spacers comprise SiN between the SiBNO and the transistor gate, where the chemical formulas list primary constituents rather than specific stoichiometries. 
     
     
         3 . The integrated device of  claim 1  wherein the sidewall spacers comprise SiN and SiBN between the SiBNO and the transistor gate, where the chemical formulas list primary constituents rather than specific stoichiometries. 
     
     
         4 . The integrated device of  claim 3  wherein the SiBN comprises a boron concentration within a range of from about 20 atomic percent to about 30 atomic percent. 
     
     
         5 . The integrated device of  claim 3  wherein the SiBNO comprises a boron concentration within a range of from about 20 atomic percent to about 30 atomic percent. 
     
     
         6 . The integrated device of  claim 3  wherein the SiBNO comprises a boron concentration within a range of from about 20 atomic percent to about 30 atomic percent; and
 wherein the SiBN comprises a boron concentration within a range of from about 20 atomic percent to about 30 atomic percent. 
 
     
     
         7 . The integrated device of  claim 3  wherein the SiN is between the SiBN and the SiBNO. 
     
     
         8 . The integrated device of  claim 7  wherein the SiN is thinner than the SiBN and the SiBNO. 
     
     
         9 . The integrated device of  claim 1  wherein the sidewall spacers comprise:
 a first layer of SiN along the sidewalls of transistor gate; 
 a layer of SiBN over the first layer of SiN; 
 a second layer of SiN over the layer of SiBN; and 
 a layer of SiBNO over the second layer of SiN; and 
 wherein the chemical formulas list primary constituents rather than specific stoichiometries. 
 
     
     
         10 . The integrated device of  claim 1  further comprising halo regions and/or LDD regions within the semiconductor base and under the sidewall spacers. 
     
     
         11 . An integrated device, comprising:
 a first transistor gate over a first region of a semiconductor base;   first sidewall spacers along sidewalls of the first transistor gate; the first sidewall spacers comprising SiBNO, where the chemical formula lists primary constituents rather than a specific stoichiometry; the first sidewall spacers having a first thickness;   a second transistor gate over a second region of the semiconductor base;   second sidewall spacers along sidewalls of the second transistor gate; the second sidewall spacers having a second thickness which is less than the first thickness;   first source/drain regions within the semiconductor base and operatively proximate the first transistor gate; and   second source/drain regions within the semiconductor base and operatively proximate the second transistor gate.   
     
     
         12 . The integrated device of  claim 11  wherein the SiBNO comprises a boron concentration within a range of from about 20 atomic percent to about 30 atomic percent. 
     
     
         13 . The integrated device of  claim 11  wherein the first sidewall spacers comprise multiple layers between the SiBNO and the first transistor gate; and wherein the second sidewall spacers comprise the multiple layers but do not comprise the SiBNO. 
     
     
         14 . The integrated device of  claim 13  wherein the multiple layers include SiN and SiBN, where the chemical formulas list primary constituents rather than specific stoichiometries. 
     
     
         15 . The integrated device of  claim 13  wherein the multiple layers include a layer of SiBN sandwiched between two layers of SiN, where the chemical formulas list primary constituents rather than specific stoichiometries. 
     
     
         16 . The integrated device of  claim 15  wherein the SiBNO is outward of, and directly against, one of the layers of SiN. 
     
     
         17 . The integrated device of  claim 11  wherein:
 a first transistor comprises the first transistor gate and the first source/drain regions; 
 a second transistor comprises the second transistor gate and the second source/drain regions; 
 the first transistor is one of a plurality of substantially identical first transistors formed at a first pitch; and 
 the second transistor is one of a plurality of substantially identical second transistors formed at a second pitch, with the second pitch being less than the first pitch. 
 
     
     
         18 . The integrated device of  claim 17  wherein:
 a memory array is over a region of the semiconductor base; 
 the memory array has memory cells; 
 wordlines and bitlines extend across the memory array to address the memory cells; 
 the wordlines are coupled with first circuitry which comprises the first transistors; and 
 the bitlines are coupled with second circuitry which comprises the second transistors. 
 
     
     
         19 . The integrated device of  claim 11  further comprising halo regions and/or LDD regions within the semiconductor base and under the first sidewall spacers. 
     
     
         20 . The integrated device of  claim 11  further comprising halo regions and/or LDD regions within the semiconductor base and under the second sidewall spacers.