Crack structures, tunneling junctions using crack structures and methods of making same

Abstract

A method of making a crack structure on a substrate, and usable as a tunnelling junction structure in a nanogap device. Such nanogap devices are in turn usable in a number of applications, notably in devices for so called quantum sequencing of DNA molecules. The method includes the controlled fracture or release of a patterned layer under built-in stress, thereby forming elements, e.g. cantilevering parts or electrodes, separated by nanogaps, so-called crack structures, or crack-junctions (CJs). The width of the crack-defined nanogap is controlled by locally release-etching the film at a notched bridge that is patterned in the film. The built-in stress contributes to forming the crack and defining of the width of the crack-defined nanogap. Further, by design of the length of the bridge in a range between sub-μπι to >25μαι, the separation between the elements, defined by the width of the crack-defined nanogaps, can be controlled for each individual crack structure from <2 nm to >100 nm. The nanogaps can be used for tunneling devices in combination with nanopores for DNA, RNA or peptides sequencing.

1 . A method of forming a crack structure on a substrate, comprising the steps of:
 providing a substrate;   providing a sacrificial layer on the substrate;   providing a layer of one or more selected material(s) on the sacrificial layer, such that there will be a built-in stress in the material(s);   patterning the layer of material(s) to provide a bridge, preferably elongated, having at least one stress concentration structure, preferably in the form of a notch or two notches located opposite each other along longsides of said bridge or as a groove extending across the bridge;   forming a crack at the stress concentration structure(s), wherein the width of the crack-defined gap is predetermined by the length of the bridge and the built-in stress;   etching away the material beneath at least part of the bridge.   
     
     
         2 . The method according to  claim 1 , wherein the crack formation occurs i) before etching away the sacrificial layer, ii) during the etching away of the sacrificial layer, or iii) after the etching away of the sacrificial layer. 
     
     
         3 . The method according to  claim 1 , wherein the built-in stress in the one or more selected material(s) is achieved by the selected material(s) having a different coefficient of thermal expansion than the substrate material, and wherein the deposition of the material is performed at temperature (s) that is different from the temperature at which the crack is formed. 
     
     
         4 . The method according to  claim 1 , wherein the substrate is made from a material selected from the group consisting of Si, silicon carbide, glass, quartz, sapphire, GaAs, GaN, InP, and polymer, in particular the substrate can be a single crystal Si wafer containing CMOS integrated circuits. 
     
     
         5 . The method according to  claim 1 , wherein the sacrificial material is selected from the group consisting of Al 2 O 3 , Si, SiO2, SiN, Al, single or few-layer graphene, and polymer, preferably provided by deposition techniques including, any of atomic layer deposition (ALD), sputtering, evaporation, chemical vapor deposition (CVD), layer transfer, spray coating, spin coating, and epitaxial growth. 
     
     
         6 . The method according to  claim 1 , wherein the patterning to obtain the notched bridge comprises lithography involving masking and etching. 
     
     
         7 . The method according to  claim 1 , wherein the layer of selected material(s) comprises a stacked structure of one or several electrically conductive layers separated by one or several dielectric layers and, wherein the conductive material preferably consisting of gold, platinum, single or few-layer graphene, titanium nitride, and superconducting materials, preferably provided by deposition techniques including, any of atomic layer deposition (ALD), sputtering, evaporation, chemical vapor deposition (CVD), layer transfer, spray coating, spin coating, and epitaxial growth. 
     
     
         8 . A crack structure on a substrate, comprising
 a substrate ( 12 ;  34 );   a spacer material layer ( 14 ;  28 ) on the substrate having at least one open space; a layer ( 16 ;  26 ,  28 ) of one or more selected material(s) provided on the spacer material ( 14 ;  28 ), the layer being patterned to exhibit a crack-defined gap ( 22 ) between two cantilevering parts ( 18   a ,  18   b ) extending across said open space, wherein the width of the crack-defined gap is predetermined by the length of the cantilevering parts and by the built-in stress;   optionally said cantilevering parts being collapsed onto the substrate.   
     
     
         9 . The crack structure according to  claim 8 , wherein the layer of selected material(s) comprises a stacked structure of one or several electrically conductive layers separated by one or several dielectric layers and, wherein the conductive material preferably consisting of gold, platinum, single or few-layer graphene, titanium nitride, and superconducting materials. 
     
     
         10 . The crack structure according to  claim 8 , wherein the substrate is made from a material selected from the group consisting of Si, silicon carbide, glass, quartz, sapphire, GaAs, GaN, InP, and polymer, in particular the substrate can be a single crystal Si wafer containing CMOS integrated circuits. 
     
     
         11 . The crack structure according to  claim 8 , wherein the spacer material is selected from the group consisting of Al 2 O 3 , Si, SiO2, SiN, Al, single or few-layer graphene, and polymer, preferably provided by deposition techniques including, any of atomic layer deposition (ALD), sputtering, evaporation, chemical vapor deposition (CVD), layer transfer, spray coating, spin coating, and epitaxial growth. 
     
     
         12 . The crack structure according to  claim 8 , wherein the width of the crack-defined gap is less than 100 nm wide, preferably less than 3 nm wide thereby enabling a tunnelling junction. 
     
     
         13 . A method of making a tunnelling device for nanopore sequencing, comprising the steps of:
 providing a substrate;   making a membrane covering an opening in said substrate;   making a pore in said membrane the size of the pore being in the nm range, preferably <50 nm in diameter, such as 2-40 nm;   depositing a sacrificial material layer on at least the membrane side of the substrate;   depositing a layer of one or more selected material(s) on the sacrificial layer on at least one side of the substrate including at least one electrically conductive material, such that there will be a built-in stress in the material(s);   patterning the layer(s) of selected material(s) to provide an elongated electrode bridge having at least one stress concentration structure, preferably a notch or notches located opposite each other along longsides of said electrode bridge or as grooves extending across the bridge;   forming a crack at the stress concentration structure(s), wherein the width of the crack-defined gap is predetermined by the length of the bridge and the built-in stress;   etching away the sacrificial layer beneath at least part of the bridge.   
     
     
         14 . The method according to  claim 13 , wherein the crack formation occurs i) before etching away the sacrificial layer, ii) during the etching away of the sacrificial layer, or iii) after the etching away of the sacrificial layer. 
     
     
         15 . The method according to  claim 13 , or H, wherein the pore and the stress concentration pattern are placed so that the crack in the bridge extends across the pore. 
     
     
         16 . The method according to  claim 13 , comprising collapsing the crack structure electrodes over the pore such that the free ends of the cantilevering electrodes contact the substrate thereby covering the pore such that the free ends of the cantilevering electrodes form a gap entrance to the pore. 
     
     
         17 . The method according to  claim 13 , comprising before etching away the sacrificial material
 depositing a further sacrificial material layer on the electrode material layer, depositing a further layer of one or more selected material(s) on said   further sacrificial material layer;   patterning said further layer of selected material(s) to define a further elongated bridge having at least one stress concentration structure, preferably a notch or notches located opposite each other along longsides of said electrode bridge or as grooves extending across the bridge, and said further bridge being oriented perpendicularly or rotated by another suitable angle to the said electrode bridge such that the future cracks are crossing.   
     
     
         18 . The method according to  claim 13 , comprising after etching away the sacrificial material
 i) depositing a further sacrificial material layer on the electrode material layer,   ii) depositing a further layer of one or more selected material(s) on said further sacrificial material layer;   iii) patterning said further layer of selected material(s) to define a further elongated bridge having at least one stress concentration structure, preferably a notch or notches located opposite each other along longsides of said electrode bridge or as grooves extending across the bridge, and said further bridge being oriented perpendicularly or rotated by another suitable angle to said bridge in a way the future cracks are crossing   iv) etching away sacrificial material at least beneath part of one of the bridges   v) forming a crack at the stress concentration structure(s), wherein the width of the crack-defined gap is predetermined by the length of the bridge and the built-in stress.   
     
     
         19 - 25 . (canceled)