Semiconductor Device Having Features to Prevent Reverse Engineering

Abstract

An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.

What is claimed is: 
     
         1 . An electronic device comprising:
 a first layer located at least partially over a base layer;   a second layer located at least partially over the first layer;   a first metal layer located at least partially over the second layer; and   a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.   
     
     
         2 . The device of  claim 1  wherein at least one gate connection is a floating gate. 
     
     
         3 . The device of  claim 1  wherein the first layer is an oxide layer. 
     
     
         4 . The device of  claim 1  wherein the second layer is a polysilicon layer. 
     
     
         5 . The device of  claim 1  wherein the base layer includes a diffusion layer. 
     
     
         6 . An electronic device comprising:
 a base layer;   a first layer located at least partially over the base layer;   a second layer located at least partially over the first layer;   a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and   a second metal layer located at least partially over the first metal layer, wherein the second metal layer is floating and one or more gate connection is connected to the second metal layer, wherein exposing the second metal layer to an ion beam results in at least one gate failure.   
     
     
         7 . The electronic device of  claim 6  wherein exposing the second metal layer to an ion beam results in at least one gate breakdown and creates at least one short between the gate, a source, and a drain of floating gate device. 
     
     
         8 . The electronic device of  claim 6  wherein the first layer is an oxide layer. 
     
     
         9 . The electronic device of  claim 6  wherein the second layer is a polysilicon layer. 
     
     
         10 . The electronic device of  claim 6  wherein the base layer includes a diffusion layer. 
     
     
         11 . An electronic circuit comprising:
 a plurality of devices having connected floating gates; and   a metal layer connected to the connected floating gates,   wherein exposing the metal layer to an ion beam results in the failure of at least one of the plurality of devices.   
     
     
         12 . The electronic circuit of  claim 11  wherein the plurality of devices comprise active devices, the active devices consisting of N-type devices. 
     
     
         13 . The electronic circuit of  claim 11  wherein the plurality of devices comprise active devices, the active devices consisting of P-type devices. 
     
     
         14 . The electronic circuit of  claim 11  wherein the metal layer is a top layer. 
     
     
         15 . An electronic device comprising:
 a base layer;   a first layer located at least partially over the base layer;   a second layer located at least partially over the first layer;   a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer;   a second metal layer located at least partially over the first metal layer, wherein the second metal layer is floating and one or more gate connection is connected to the second metal layer,   a third metal layer located at least partially over the second metal layer and separated from the second metal layer by a dielectric, wherein exposing the third metal layer to an ion beam results in at least one gate failure of the gates connected to the second metal layer.   
     
     
         16 . The electronic device of  claim 15  wherein the dielectric is a passivation layer. 
     
     
         17 . The electronic device of  claim 15  further comprising a fourth metal layer located at least partially over the third metal layer, wherein exposing the fourth metal layer to an ion beam results in at least one gate failure of the gates connected to the second metal layer.