Systems and methods for optimizing nested loop instructions in pipeline processing stages within a machine perception and dense algorithm integrated circuit

Abstract

In one embodiment, a method for improving a performance of an integrated circuit includes implementing one or more computing devices executing a compiler program that: (i) evaluates a target instruction set intended for execution by an integrated circuit; (ii) identifies one or more nested loop instructions within the target instruction set based on the evaluation; (iii) evaluates whether a most inner loop body within the one or more nested loop instructions comprises a candidate inner loop body that requires a loop optimization that mitigates an operational penalty to the integrated circuit based on one or more executional properties of the most inner loop instruction; and (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control, at runtime, an execution and a termination of the most inner loop body thereby mitigating the operational penalty to the integrated circuit.

What is claimed: 
     
         1 . A method for improving a performance of an integrated circuit, the method comprising:
 implementing one or more computing devices executing a compiler program that:
 (i) evaluates a target instruction set; 
 (ii) identifies one or more loop instructions within the target instruction set based on the evaluation; 
 (iii) evaluates whether an inner loop body within the one or more loop instructions comprises a candidate inner loop body requiring a loop optimization that mitigates an operational penalty to an integrated circuit based on one or more executional properties of the inner loop instruction; and 
 (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control an execution and a termination of the inner loop body thereby mitigating the operational penalty. 
   
     
     
         2 . A system for improving a performance of an integrated circuit, the system comprising:
 one or more computing devices executing a compiler program that:
 (i) evaluates a target instruction set; 
 (ii) identifies one or more loop instructions within the target instruction set based on the evaluation; 
 (iii) evaluates whether an inner loop body within the one or more loop instructions comprises a candidate inner loop body requiring a loop optimization that mitigates an operational penalty to an integrated circuit based on one or more executional properties of the inner loop instruction; and 
 (iv) implements the loop optimization that modifies the target instruction set to include loop optimization instructions to control an execution and a termination of the inner loop body thereby mitigating the operational penalty.