Axi interconnect module communication network platform

Abstract

Implementations described and claimed herein provide methods and systems for routing data, message, and register access transactions through common ports in an on-chip interface interconnect module while supporting Quality of Service (QoS) and maintaining fair data throughput. In one implementation, a System on Chip system includes an AXI interconnect module to route data, message, and register access transactions via common ports in the AXI interconnect module. The system may include at least one master circuit module configured to initiate data transaction, wherein the at least one master circuit module behaves as a slave to receive message transactions and register access transactions. The system may include at least one slave circuit module configured to respond to data transactions, wherein the at least one slave circuit module behaves as a master to initiate message transactions. The system may use QoS signaling as a priority indicator to prioritize the transactions.

1 .- 14 . (canceled) 
     
     
         15 . A method, comprising:
 initiating an on-chip interface interconnect module transaction in at least one master circuit module;   decoding a write address field with an on-chip interface interconnect module to route the on-chip interface interconnect module transaction to at least one slave circuit module, the on-chip interface interconnect module having a plurality of common ports and configured to route data transactions, message transactions, and register access transactions via the common ports; and   decoding the on-chip interconnect module interface transaction as one of a data transaction, a message transaction, and a register access transaction in the at least one slave circuit module.   
     
     
         16 . The method of  claim 15 , further comprising:
 receiving user defined signals from the on-chip interface interconnect module; and   assigning a priority value for the on-chip interface interconnect module transaction based on the user defined signals.   
     
     
         17 . The method of  claim 15 , further comprising:
 receiving Quality of Service (QoS) signals from the on-chip interface interconnect module; and   assigning a priority value for the on-chip interface interconnect module transaction based on the QoS signals.   
     
     
         18 . The method of  claim 15 , further comprising:
 assigning a transaction priority value for the on-chip interface interconnect module transaction via an arbitration scheme.   
     
     
         19 . The method of  claim 18 , wherein the arbitration scheme includes a weighted round robin operation that assigns a weight to the transaction correlating to the priority value. 
     
     
         20 . The method of  claim 19 , further comprising:
 assigning a high weight to the data transaction;   assigning a medium weight to the message transaction; and   assigning a low weight to the register access transaction.   
     
     
         21 . The method of  claim 15 , further comprising:
 responding to the data transaction with the at least one slave circuit module, wherein the at least one slave circuit module behaves as a master to initiate message transactions.   
     
     
         22 . The method of  claim 15 , wherein the on-chip interface interconnect module comprises an Advanced eXtensible interface interconnect module. 
     
     
         23 . A system comprising:
 an on-chip interface interconnect module configured to:
 initiate an on-chip interface interconnect module transaction in at least one master circuit module, 
 decode a write address field with the on-chip interface interconnect module to route the on-chip interface interconnect module transaction to at least one slave circuit module, and 
 decode the on-chip interconnect module interface transaction as one of a data transaction, a message transaction, and a register access transaction in the at least one slave circuit module 
   wherein the on-chip interface connect module comprises a plurality of common ports of the on-chip interface connect module configured to route the data transactions, the message transactions, and register access transactions via the plurality of common ports.   
     
     
         24 . The system of  claim 23 , wherein the on-chip interface interconnect module further comprises an Advanced eXtensible interface interconnect module network. 
     
     
         25 . The system of  claim 23 , further comprising:
 at least one master circuit module configured to initiate the data transaction, wherein the at least one master circuit module behaves as a slave to receive message transactions and register access transactions.   
     
     
         26 . The system of  claim 23 , further comprising:
 at least one slave circuit module configured to respond to the data transactions, wherein the at least one slave circuit module behaves as a master to initiate message transactions.   
     
     
         27 . The system of  claim 23 , wherein Quality of Service (QoS) signaling is used as a priority indicator to prioritize the data transactions, the message transactions, and the register access transactions. 
     
     
         28 . The system of  claim 27 , wherein the QoS signaling is transferred through write and read address channels. 
     
     
         29 . The system of  claim 27 , wherein the on-chip interconnect module interface supports two 4-bit QoS signaling. 
     
     
         30 . The system of  claim 23 , further comprising:
 a weighted round robin arbitration module operative to implement a weighted round robin arbitration method by dividing the data transactions, message transactions, and register transactions into different respective service classes and allocating port bandwidth of the common ports based on weights assigned to each of the service classes.   
     
     
         31 . The system of  claim 30 , wherein Quality of Service (QoS) signaling is used as a priority indicator to the weighted round robin arbitration module for the dividing the data transactions, message transactions, and register transactions into different respective service classes to prioritize the data transactions, the message transactions, and the register access transactions in relation to the allocation of the port bandwidth of the common ports based on weights assigned to each of the service classes.