Systems and methods for stalling host processor

Abstract

Systems and methods for stalling a host processor. In some embodiments, the host processor may be caused to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction. The host processor may be prevented from completing the one or more selected transactions, to thereby stall the host processor.

What is claimed is: 
     
         1 . A method for stalling a host processor, the method comprising acts of:
 causing the host processor to initiate one or more selected transactions, wherein the one or more selected transactions comprise a bus transaction; and   preventing the host processor from completing the one or more selected transactions, to thereby stall the host processor.   
     
     
         2 . The method of  claim 1 , wherein:
 the host processor communicates with a downstream component via a communication path;   the bus transaction is initiated on a bus that is outside the communication path between the host processor and the downstream component; and   the act of preventing the host processor from completing the one or more selected transactions is performed in response to determining that the downstream component is falling behind the host processor.   
     
     
         3 . The method of  claim 1 , wherein:
 the bus transaction is selected from a group consisting of: an instruction bus transaction and a data bus transaction.   
     
     
         4 . The method of  claim 2 , wherein:
 the bus transaction is selected from a group consisting of: a load operation and a store operation.   
     
     
         5 . The method of  claim 1 , wherein:
 the act of causing the host processor to initiate one or more selected transactions comprises asserting an interrupt to cause the host processor to initiate the bus transaction, which comprises an operation with respect to a selected address.   
     
     
         6 . The method of  claim 5 , wherein:
 the interrupt comprises a non-maskable interrupt.   
     
     
         7 . The method of  claim 5 , wherein:
 the selected address comprises an interrupt vector address corresponding to the interrupt; and   the act of preventing the host processor from completing the bus transaction comprises preventing the host processor from loading, from the interrupt vector address, one or more instructions of an interrupt handler corresponding to the interrupt.   
     
     
         8 . The method of  claim 7 , further comprising an act of:
 storing, at the interrupt vector address, one or more instructions that, when executed by the host processor, cause the host processor to return from the interrupt.   
     
     
         9 . The method of  claim 7 , wherein:
 the interrupt comprises a first interrupt; and   the method further comprises acts of:
 determining whether a second interrupt has been asserted after the first interrupt; and 
 in response to determining that a second interrupt has been asserted after the first interrupt, storing, at the interrupt vector address, one or more instructions that, when executed by the host processor, cause the host processor to jump to an interrupt handler corresponding to the second interrupt. 
   
     
     
         10 . The method of  claim 5 , wherein:
 the selected address comprises an address of a selected register; and   the act of preventing the host processor from completing the bus transaction comprises preventing the host processor from storing a value to the selected register.   
     
     
         11 . The method of  claim 1 , further comprising an act of:
 detecting a trigger to stall the host processor, wherein the act of causing the host processor to initiate one or more selected transactions is performed in response to detecting the trigger to stall the host processor.   
     
     
         12 . The method of  claim 11 , further comprising an act of:
 processing metadata associated with instructions executed by the host processor to check if the instructions are to be allowed, wherein the act of detecting a trigger to stall the host processor comprises determining that the metadata processing is falling behind the host processor's execution.   
     
     
         13 . The method of  claim 12 , further comprising acts of:
 storing a result of the host processor's execution in a result queue while an instruction that produced the result is being checked; and   in response to determining that the instruction is to be allowed, writing the result to an application memory, wherein the act of detecting a trigger to stall the host processor comprises determining that the result queue is filled to a selected threshold level.   
     
     
         14 . The method of  claim 12 , further comprising an act of:
 storing instructions to be checked in an instruction queue, wherein the act of detecting a trigger to stall the host processor comprises determining that the instruction queue is filled to a selected threshold level.   
     
     
         15 . The method of  claim 12 , further comprising an act of:
 allowing the host processor to complete the one or more selected transactions in response to determining that the metadata processing is no longer behind the host processor's execution.   
     
     
         16 . The method of  claim 1 , wherein:
 the act of causing the host processor to initiate one or more selected transactions comprises inserting, into object code, one or more instructions that, when executed by the host processor, cause the host processor to initiate the one or more selected transactions.   
     
     
         17 . The method of  claim 16 , wherein:
 the one or more instructions are inserted into the object code at a frequency selected based on a capacity of a downstream component that consumes outputs of the host processor.   
     
     
         18 . The method of  claim 17 , wherein:
 the capacity of the downstream component is selected based on a quantum of a preemptive operating system.   
     
     
         19 . The method of  claim 17 , wherein:
 the frequency is selected according to a probability distribution.   
     
     
         20 . A method for stalling transactions on a first bus along a communication path between an upstream component and a downstream component, the method comprising acts of:
 causing the upstream component to initiate a transaction on a second bus, wherein the second bus is outside the communication path between the upstream component and the downstream component; and   stalling the transaction on the second bus to thereby stall the upstream component.   
     
     
         21 . The method of  claim 20 , wherein:
 the first bus does not provide a native stall signal.   
     
     
         22 . The method of  claim 21 , wherein:
 the act of causing the upstream component to initiate a transaction on a second bus is performed in response to detecting that the downstream component is falling behind the upstream component.   
     
     
         23 . A system comprising circuitry and/or one or more processors programmed by executable instructions, wherein the circuitry and/or the one or more programmed processors are configured to perform the method of any of  claims 1 - 22 . 
     
     
         24 . At least one computer-readable medium having stored thereon at least one netlist for the circuitry of  claim 23 . 
     
     
         25 . At least one computer-readable medium having stored thereon at least one hardware description that, when synthesized, produces the at least one netlist of  claim 24 . 
     
     
         26 . The at least one computer-readable medium of  claim 25 , wherein the at least one hardware description is in an encrypted form. 
     
     
         27 . At least one computer-readable medium having stored thereon the executable instructions of  claim 23 .