Solid state drive architectures

Abstract

A solid state drive (SSD) includes dynamic random access memory (DRAM), flash memory, and a solid state drive (SSD) controller. The solid state drive (SSD) also includes a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM. The SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.

What is claimed is: 
     
         1 . A solid state drive (SSD) comprising:
 dynamic random access memory (DRAM);   flash memory;   a solid state drive (SSD) controller; and   a peripheral component interconnect express (PCIe) bus to connect the SSD to a computing device such that a central processing unit (CPU) of the computing device exclusively reads data from, and writes data to, the DRAM,   wherein the SSD controller writes data to the flash memory from the DRAM independently of received commands from the computing device.   
     
     
         2 . The SSD of  claim 1 , wherein the SSD controller comprises:
 a non-volatile memory express (NVMe) controller to receive commands from the computing device to access the SSD;   a command block to receive and store the commands, wherein a command includes a logical block address and a command word;   a memory manager to manage data transfer into and out of the DRAM based on a mapping between the logical block address of the command and a pointer to a location in the DRAM;   a logical flash controller to manage data transfer between the SSD and the computing device;   at least one flash interface controller to buffer data to be written to multiple flash die from the DRAM; and   a flash controller per flash interface controller paired with a flash die to manage data access into and out of the flash die.   
     
     
         3 . The SSD of  claim 2 , wherein the at least one flash interface controller comprises multiple flash interface controllers. 
     
     
         4 . The SSD of  claim 3 , wherein multiple flash die are written to in parallel. 
     
     
         5 . The SSD of  claim 2 , wherein the SSD controller further comprises a DRAM controller to manage data access to the DRAM. 
     
     
         6 . The SSD of  claim 2 , wherein the flash interface controller maps the logical block address to locations on corresponding flash die. 
     
     
         7 . The SSD of  claim 1 , in which data access to the DRAM is implemented at full interface speed. 
     
     
         8 . A method, comprising:
 receiving from a computing device, a command to access a solid state drive (SSD), wherein the command includes a logical block address and a command word;   storing the command in a command block of an SSD controller;   determining, from a logical record (LR) table stored in a memory manager of the SSD controller, whether the logical block address maps to a pointer to a location on dynamic random access memory (DRAM); and   when the logical block address maps to a pointer in the DRAM, executing the command in the DRAM based on the mapping, while preventing access of the computing device to flash memory of the SSD.   
     
     
         9 . The method of  claim 8 , wherein:
 the command is a read command; and   the method further comprises:
 determining from the LR table, with the memory manager, if data associated with the command word is stored in DRAM; 
 when the data associated with the command word is stored in DRAM, transferring the data from the DRAM to the computing device; and 
 when the data associated with the command word is not stored in DRAM:
 sending the command word to a flash interface controller; 
 determining at the flash interface controller a location on the flash memory where the data is stored; and 
 transferring the data from the flash memory to the computing device. 
 
   
     
     
         10 . The method of  claim 9 , wherein data is stored on the DRAM in 32k packets. 
     
     
         11 . The method of  claim 8 , wherein:
 the command is a write command; and   the method further comprises:
 when the logical block address maps to a location on the DRAM, storing data associated with the command word in DRAM; and 
 when the logical block address does not map to a location on the DRAM:
 generating a mapping between the logical block address of the command and a new unused location on the DRAM; and 
 storing the data associated with the command on the DRAM in the new unused location; and 
 
 reporting to the computing device that the write command is complete. 
   
     
     
         12 . The method of  claim 8 , further comprising:
 holding data associated with the command in DRAM;   determining when the DRAM has a threshold amount of full blocks; and   when the DRAM has the threshold amount of full blocks, transferring the full blocks to the flash memory, wherein the full blocks are transferred to the flash memory independent of any received command.   
     
     
         13 . The method of  claim 12 , wherein transferring the full blocks to the flash memory comprises:
 dividing the data in the full blocks into various portions;   buffering the various portions in different flash interface controllers; and   for each flash interface controller:
 sequentially initiating writes to each corresponding flash die via a flash controller coupled to a flash die. 
   
     
     
         14 . The method of  claim 13 , wherein:
 after a write has been initialized on a first flash die, initiating a write on a second flash die before the write to the first flash die is complete; and   when data remains in the buffer and the write on the first flash die has terminated, initiating another sequential write on the first flash die.   
     
     
         15 . The method of  claim 14 , wherein writes to each flash die are at three or four page increments. 
     
     
         16 . A solid state drive (SSD) comprising:
 dynamic random access memory (DRAM);   flash memory comprising:
 multiple flash die; 
 at least one flash interface controller to buffer data to be written to a subset of the multiple flash die from the DRAM; and 
 a flash controller per flash interface controller and paired with a flash die to manage data access into and out of the flash die, 
   a peripheral component interconnect express (PCIe) bus coupling the SSD to a computing device; and   a solid state drive (SSD) controller comprising:
 a non-volatile memory express (NVMe) controller to receive commands to access the SSD; 
 a command block to receive and store the commands, wherein a command includes a logical block address and a command word; 
 a memory manager to manage data transfer into and out of the DRAM based on a mapping between the logical block address of the command and a pointer to a location in the DRAM; 
 a logical flash controller to manage data transfer between the SSD and the computing device; 
 wherein less than all writes to the SSD are written to the flash memory. 
   
     
     
         17 . The SSD of  claim 16 , wherein the DRAM is the only memory accessible by the computing device. 
     
     
         18 . The SSD of  claim 16 , wherein the NVMe controller receives multiple commands and stores the multiple commands in a command buffer of the command block. 
     
     
         19 . The SSD of  claim 16 , wherein the command block sends a record of execution of the command. 
     
     
         20 . The SSD of  claim 16 , wherein pages of the flash die are identified as having errors and eliminated from a block while other pages in the block remain in use to increase the lifetime of the flash memory by at least  10  times that of flash memory that eliminates an entire sector when an error is detected in a page within the sector.