Systems and methods of detecting power bugs
Abstract
Embodiments of the present invention provide a system and methods for detecting power bugs. In one embodiment, a computer-implemented method for analyzing a computer code includes generating a control flow graph for at least a portion of the computer code at a processor. The method further includes identifying power bugs by traversing the control flow graph if the control flow graph exits without performing a function call to deactivate power to any component of a device configured to execute computer executable instructions based on the computer code after performing a function call to activate power.
Claims
exact text as granted — not AI-modified1 - 19 . (canceled)
20 . A computer-implemented method for analyzing a computer code, the method comprising:
at a processor, generating a control flow graph for at least a portion of the computer code; and identifying power bugs by detecting if the control flowgraph or a variation of the control flow graph exits without performing a function call to deactivate power to any component of a device configured to execute computer executable instructions based on the computer code after performing a function call to activate power, wherein the step of identifying power bugs comprises applying a forward analysis, a backward analysis, or a combination thereof.
21 . The method of claim 20 , further comprising generating an error message if the control flowgraph exits without performing a function call to deactivate power to any component.
22 . The method of claim 21 , further comprising storing the error message in a non-transitory memory medium.
23 . The method of claim 20 , wherein the computer executable instructions are configured to run on a power constrained device, wherein the function call to activate power comprises a function call to prevent the power constrained device from going to sleep, and wherein the function call to deactivate power comprises a function call to re-allow the power constrained device to go to sleep.
24 . The method of claim 20 , further comprising:
receiving the computer code; and removing the identified power bugs.
25 . The method of claim 24 , further comprising:
after removing the identified power bugs, generating the computer executable instructions by compiling the computer code if the computer code exits after performing a function call to deactivate power to any component previously activated; and storing the computer executable instructions in a non-transitory memory medium.
26 . The method of claim 25 , further comprising:
providing an application comprising the computer executable instructions to a user device at an online market place.
27 . The method of claim 20 , wherein the backward dataflow analysis, comprising:
applying a reaching definitions analysis to identify any mismatch in definitions relating to function calls for activating or deactivating power.
28 . The method of claim 27 , wherein the control flow graph is a reverse control flow graph in which edges of the control flow graph are reversed, wherein applying the reaching definitions analysis further comprises:
identifying steps in the reverse control flow graph relating to function calls for activating or deactivating power, defining a power variable for each step with a function call for deactivation and for each step that is an EXIT, assigning a first binary value to the power variable for each EXIT and assigning an opposite second binary value to the power variable for each function call for deactivation, generating a set of definitions of the power variable reaching each function call for activation in the reverse control flow graph, and identifying a power bug if any definition of the first binary value is identified in the set of definitions of the power variable at any function call for activation.
29 . The method of claim 20 , wherein applying the backward analysis comprises applying a live variable analysis, an available expressions analysis, a constant propagation analysis, a depth first search analysis, a breadth first search analysis, or a combination thereof.
30 . The method of claim 20 , wherein applying the forward analysis comprises:
applying a breadth first search analysis to the control flow graph.
31 . The method of claim 20 , wherein the forward analysis comprises:
applying a constant propagation analysis to identify any mismatch in definitions relating to function calls for activating or deactivating power.
32 . The method of claim 20 , wherein the computer code is configured to execute as a single threaded process.
33 . The method of claim 20 , wherein generating the control flow graph comprises:
generating individual control flow graph for each event handler in the computer code comprising a plurality of event handlers; and stitching together the individual control flow graphs.
34 . The method of claim 20 , wherein computer code is configured to execute as a multi-threaded application and the control flow graph is configured for the multithreaded application.
35 . The method of claim 34 , wherein generating the control flow graph further comprises:
generating individual control flow graph for each thread; connecting a fork spawning each thread with an ENTRY block of the individual control flow graph for that thread; and connecting an EXIT block of the individual control flow graph for that thread with a join node or with another ENTRY block of another individual control flow graph of another thread.
36 . The method of claim 20 , where the variation of the control flow graph is a program graph that retains path information of the original control flow graph, wherein the reachability from any node that contains a function call for activation to any node that contains a function call for deactivation and to the EXIT node in the original control flow graph is preserved.
37 . A computing device comprising:
a processor configured to execute a debugging tool, the debugging tool configured to: generate a control flow graph for at least a portion of a computer code, and identify power bugs by detecting if the control flow graph exits without performing a function call for deactivating power to any component of a device configured to execute computer executable instructions based on the computer code by traversing the control flow graph after performing a function call to activate power,
wherein the step of identify power bugs comprises applying a forward analysis, a backward analysis, or a combination thereof.
38 . The computing device of claim 37 , wherein apply the backward analysis comprises:
apply a reaching definitions analysis to identify any mismatch in definitions relating to function calls for activating or deactivating power.
39 . The computing device of claim 38 , wherein the control flow graph is a reverse control flow graph in which edges of the control flow graph are reversed, the method further comprising, wherein apply the reaching definitions analysis comprises:
identify steps in the reverse control flow graph relating to function calls for activating or deactivating power, define a power variable for each step with a function call for deactivation and for each step that is an EXIT, assign a first binary value to the power variable for each EXIT and assigning an opposite second binary value to the power variable for each function call for deactivation, generate a set of definitions of the power variable reaching each function call for activation in the reverse control flow graph, and identify a power bug if any definition of the first binary value is identified in the set of definitions of the power variable at any function call for activation.Join the waitlist — get patent alerts
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