Image processing apparatus using artificial intelligence super-resolution circuit and follow-up resize circuit for image resizing

Abstract

An image processing apparatus includes a super-resolution (SR) circuit and a resizer circuit. The SR circuit performs an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, and the SR operation is based, at least in part, on one or more artificial intelligence (AI) models. The resizer circuit performs a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and no AI model is involved in the resize operation.

What is claimed is: 
     
         1 . An image processing apparatus comprising:
 a super-resolution (SR) circuit, arranged to perform an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, and the SR operation is based, at least in part, on one or more artificial intelligence (AI) models; and   a resizer circuit, arranged to perform a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and no AI model is involved in the resize operation.   
     
     
         2 . The image processing apparatus of  claim 1 , wherein the second image comprises a plurality of pixel lines each having a plurality of pixels, and the SR circuit is further arranged to output pixels of the second image in a raster scan order, where the plurality of pixels at each pixel line are sequentially output in a left-to-right order, and the plurality of pixel lines are sequentially output in a top-to-bottom order. 
     
     
         3 . The image processing apparatus of  claim 1 , wherein an output port of the SR circuit is directly linked to an input port of the resizer circuit. 
     
     
         4 . The image processing apparatus of  claim 1 , wherein the image processing apparatus comprises no frame buffer or block buffer coupled between an output port of the SR circuit and an input port of the resizer circuit. 
     
     
         5 . The image processing apparatus of  claim 1 , further comprising:
 an image pre-processing circuit, arranged to perform an image pre-processing operation upon a fourth image to generate the first image.   
     
     
         6 . The image processing apparatus of  claim 5 , wherein the first image comprises a plurality of pixel lines each having a plurality of pixels, and the image pre-processing circuit is further arranged to output pixels of the first image in a raster scan order, where the plurality of pixels at each pixel line are sequentially output in a left-to-right order, and the plurality of pixel lines are sequentially output in a top-to-bottom order. 
     
     
         7 . The image processing apparatus of  claim 5 , wherein an output port of the image pre-processing circuit is directly linked to an input port of the SR circuit. 
     
     
         8 . The image processing apparatus of  claim 5 , wherein the image processing apparatus comprises no frame buffer or block buffer coupled between an output port of the image pre-processing circuit and an input port of the SR circuit. 
     
     
         9 . The image processing apparatus of  claim 5 , wherein the image pre-processing operation comprises noise reduction. 
     
     
         10 . The image processing apparatus of  claim 1 , wherein the SR circuit and the resizer circuit are integrated in a same chip. 
     
     
         11 . An image processing apparatus comprising:
 a super-resolution (SR) circuit, arranged to perform an SR operation upon a first image to generate a second image, wherein a resolution of the second image is not lower than a resolution of the first image, the SR circuit supports fixed scaling ratios only, and any scaling ratio employed by the SR operation is selected from the fixed scaling ratios; and   a resizer circuit, arranged to perform a resize operation upon the second image to generate a third image, wherein a resolution of the third image is not lower than the resolution of the second image, and any scaling ratio employed by the resize operation is an arbitrary scaling ratio supported by the resizer circuit.   
     
     
         12 . The image processing apparatus of  claim 11 , wherein the second image comprises a plurality of pixel lines each having a plurality of pixels, and the SR circuit is further arranged to output pixels of the second image in a raster scan order, where the plurality of pixels at each pixel line are sequentially output in a left-to-right order, and the plurality of pixel lines are sequentially output in a top-to-bottom order. 
     
     
         13 . The image processing apparatus of  claim 11 , wherein an output port of the SR circuit is directly linked to an input port of the resizer circuit. 
     
     
         14 . The image processing apparatus of  claim 11 , wherein the image processing apparatus comprises no frame buffer or block buffer coupled between an output port of the SR circuit and an input port of the resizer circuit. 
     
     
         15 . The image processing apparatus of  claim 11 , further comprising:
 an image pre-processing circuit, arranged to perform an image pre-processing operation upon a fourth image to generate the first image.   
     
     
         16 . The image processing apparatus of  claim 15 , wherein the first image comprises a plurality of pixel lines each having a plurality of pixels, and the image pre-processing circuit is further arranged to output pixels of the first image in a raster scan order, where the plurality of pixels at each pixel line are sequentially output in a left-to-right order, and the plurality of pixel lines are sequentially output in a top-to-bottom order. 
     
     
         17 . The image processing apparatus of  claim 15 , wherein an output port of the image pre-processing circuit is directly linked to an input port of the SR circuit. 
     
     
         18 . The image processing apparatus of  claim 15 , wherein the image processing apparatus comprises no frame buffer or block buffer coupled between an output port of the image pre-processing circuit and an input port of the SR circuit. 
     
     
         19 . The image processing apparatus of  claim 15 , wherein the image pre-processing operation comprises noise reduction. 
     
     
         20 . The image processing apparatus of  claim 11 , wherein the SR circuit and the resizer circuit are integrated in a same chip.