Semiconductor device package with reduced stress

Abstract

A described example includes: a semiconductor device die with an active surface; the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads; at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a semiconductor device die with an active surface;   the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads;   at least a first rigid low expansion material (RLEM) covering a portion of the semiconductor device die; and   the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound and forming a packaged semiconductor device die.   
     
     
         2 . The apparatus of  claim 1 , further comprising:
 a stress sensitive component on a device side of the semiconductor device die; and   the first RLEM covering the stress sensitive component.   
     
     
         3 . The apparatus of  claim 1 , wherein the first RLEM covers a portion of a non-device side of the semiconductor device die. 
     
     
         4 . The apparatus of  claim 1 , further comprising:
 a stress sensitive component on a device side of the semiconductor device die;   the first RLEM covering the stress sensitive component; and   a second RLEM with a first side over a non-device side of the semiconductor device die.   
     
     
         5 . The apparatus of  claim 1 , further comprising at least one stress sensitive component on the semiconductor device die selected from a group consisting essentially of: a bipolar junction transistor (BJT), an analog transistor, an oscillator, a bulk acoustic wave (BAW) oscillator, a piezoelectric device, a junction field effect transistor (JFET), a metal oxide semiconductor field effect transistor (MOSFET), a thin film resistor, and a vertical capacitor. 
     
     
         6 . The apparatus of  claim 1 , further comprising
 at least one stress sensitive component on the semiconductor device die;   the stress sensitive component covered by the first RLEM; and   edges of the RLEM overlapping the stress sensitive component by at least 10 μm.   
     
     
         7 . The apparatus of  claim 1 , wherein a coefficient of thermal expansion of the RLEM is between about positive 2 ppm/° C. and negative 30 ppm/° C. 
     
     
         8 . The apparatus of  claim 1 , wherein a coefficient of thermal expansion of the RLEM is less than 2.6 ppm/° C. 
     
     
         9 . The apparatus of  claim 1 , wherein the RLEM is one selected from a group consisting essentially of: sitall, invar, quartz, diamond, graphite, Corning ULE 7972, and Corning ULE 7973. 
     
     
         10 . The apparatus of  claim 1 , wherein wire bonds electrically couple the semiconductor device die to the substrate leads. 
     
     
         11 . The apparatus of  claim 1 , wherein conductive post connects electrically couple the semiconductor device die to the substrate leads. 
     
     
         12 . The apparatus of  claim 1 , wherein solder ball bonds couple the semiconductor device die to the substrate. 
     
     
         13 . The apparatus of  claim 1 , wherein the substrate is a lead frame. 
     
     
         14 . A method, comprising:
 attaching a rigid low expansion material (RLEM) to a surface of a semiconductor device die;   covering a selected portion of the surface with the RLEM;   mounting the semiconductor device die on a package substrate that has substrate leads; and   covering the RLEM, the semiconductor device die, and a portion of the substrate leads with mold compound to form a packaged semiconductor device with RLEM.   
     
     
         15 . The method of  claim 14 , further comprising:
 coupling the semiconductor device die to leads on the package substrate with wire bonds.   
     
     
         16 . The method of  claim 14 , further comprising:
 forming conductive post connects on a device side of the semiconductor device die; and   electrically coupling the semiconductor device die to substrate leads with the conductive post connects.   
     
     
         17 . The method of  claim 14 , wherein the selected portion is a stress sensitive component on a device side of the semiconductor device die. 
     
     
         18 . The method of  claim 14 , wherein the selected portion is a non-device side of the semiconductor device die. 
     
     
         19 . The method of  claim 14 , further comprising:
 covering a stress sensitive component on a device side of the semiconductor device die with a first RLEM; and   covering a portion of a non-device side of the semiconductor device die with a second RLEM.   
     
     
         20 . A packaged semiconductor device, comprising:
 a semiconductor device die with an active surface, the semiconductor device die mounted on a package substrate with substrate leads and the semiconductor device die electrically coupled to the substrate leads;   at least a first rigid low expansion material (RLEM) covering a stress sensitive component in a portion of the active surface of the semiconductor device die; and   the first RLEM, the semiconductor device die, and a portion of the substrate leads covered with mold compound.