Systems and methods for implementing tile-level predication within a machine perception and dense algorithm integrated circuit

Abstract

Systems and methods of implementing tile-level predication of a computing tile of an integrated circuit includes identifying a plurality of distinct predicate state values for each of a plurality of distinct processing cores of the computing tile; calculating one or more summed predicate state values for an entirety of the plurality of distinct processing cores based on performing a summation operation of the plurality of distinct predicate state values; propagating the one or more summed predicate state values to an instructions generating circuit of the integrated circuit; and identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on input of the one or more summed predicate state values.

What is claimed: 
     
         1 . A method of implementing tile-level predication of a computing tile of an integrated circuit, the method comprising:
 calculating a summed predicate state value for the plurality of distinct processing cores of the computing tile based on a plurality of distinct predicate state values associated with the plurality of distinct processing cores; and   identifying, by the instructions generating circuit, a tile-level predication for the computing tile based on an input of the summed predicate state value.   
     
     
         2 . The method according to  claim 1 , further comprising:
 identifying the plurality of distinct predicate state values that includes:
 identifying a top of stack value of a distinct predicate stack associated with each of the plurality of distinct processing cores of the computing tile based on an evaluation an associated predicate condition; and 
 identifying a bit value of a distinct enablement bit associated with each of the plurality of distinct processing cores of the computing tile. 
   
     
     
         3 . The method according to  claim 2 , wherein
 the identifying the plurality of distinct predicate state values further includes:
 identifying a loop depth of a nested loop body; 
 incrementing a loop depth counter based on the identified loop depth; 
 tallying a subset of processing cores of the plurality of distinct processing cores that are in an active state for executing the nested loop body; and 
 identifying predicate state values of the subset of processing cores separately from the plurality of distinct predicate state values a remainder of the plurality of distinct processing cores that are in an inactive state for executing the nest loop body. 
   
     
     
         4 . The method according to  claim 1 , further comprising:
 executing a branch target instruction to branch around a target instruction that avoids a target set of instructions accessible to the plurality of distinct processing cores based on identifying the tile-level predication.   
     
     
         5 . The method according to  claim 1 , wherein
 the plurality of distinct predicate state values includes:
 (i) a plurality of distinct top of stack values for a plurality of distinct predicate stacks of the plurality of distinct processing cores of the computing tile; and 
 (ii) a plurality of distinct enablement bit values of the plurality of distinct processing cores of the computing tile.