US2021351963A1PendingUtilityA1

Passive linear equalizer for serial wireline receivers

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Assignee: ANALOG BITS INCPriority: Sep 11, 2019Filed: Mar 4, 2021Published: Nov 11, 2021
Est. expirySep 11, 2039(~13.2 yrs left)· nominal 20-yr term from priority
H04L 25/03878H04L 25/03885H04L 25/03146H04L 25/0272H04L 25/03127
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Claims

Abstract

Some implementations provide a passive equalizer section configured to filter an input signal, the passive equalizer section including: a first passive filter that comprises: a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, wherein the first resistor and the first reactive component are in series and connected at a first connection node; and a second passive filter that comprises: a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, wherein the second resistor and the second reactive component are in series and connected at a second connection node; and a signal mixing section comprising a plurality of transistors to mix signals with different frequency response characteristics.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . An equalizer circuit, comprising:
 a passive equalizer section coupled to at least one input node, the passive equalizer section configured to filter an input signal and including:
 a first passive circuit comprising a first resistor characterized by a first resistance, and a first reactive component characterized by a first reactance, and coupled to the at least one input node, wherein the first reactive component is coupled to the first resistor at a first connection node, and wherein the first passive circuit is disposed between the at least one input node and a first common node; and 
 a second passive circuit comprising a second resistor characterized by a second resistance, and a second reactive component characterized by a second reactance, and coupled to the at least one input node, wherein the second reactive component is coupled to the second resistor at a second connection node, and wherein the second passive circuit is disposed between the at least one input node and a second common node; 
   a signal mixing section coupled to the passive equalizer section and comprising:
 a first transistor coupled to the first passive circuit at the first connection node and configured to receive a first signal therefrom; and 
 a second transistor coupled to the second passive circuit at the second connection node and configured to receive a second signal therefrom, 
   wherein the signal mixing section is configured to:
 mix the first signal and the second signal with respective frequency response characteristics; and 
 generate an output signal.

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