Circuit to generate data signal current and display panel

Abstract

The present disclosure describes a display panel and a circuit to generate a data signal current included thereof. The circuit further comprises a signal voltage module to generate a primary signal voltage and send to a second storage capacitor in a control module to output a data signal voltage. The second storage capacitor is coupled to a first storage capacitor and a gate of a current output transistor, so that the primary signal voltage is stored at the joint node. A threshold voltage of the current output transistor, generated by a voltage compensation module, is then added on to the gate of the current output transistor, so that an output current compensated by the threshold voltage is realized.

1 . A circuit to generate a data signal current, comprising:
 a voltage circuit to generate a data signal voltage,   a control circuit to output the data signal voltage,   a compensation control circuit, a first capacitor, and   a current output transistor, wherein   the voltage circuit is connected to the control circuit, and is configured to output the data signal voltage to the control circuit; the control circuit comprises at least one second capacitor, a second terminal of the second capacitor is connected to a first power supply terminal of the circuit, and the second capacitor is configured to store the data signal voltage;   the control circuit is connected to a gate of the current output transistor, and is configured to output the data signal voltage to the gate of the current output transistor; and   the compensation control circuit is connected between the gate and a first terminal of the current output transistor; the compensation control circuit is configured to provide the gate of the output transistor with its own threshold voltage; a first terminal of the first capacitor is connected to the gate of the current output transistor, and a second terminal of the first capacitor is connected to the first power supply terminal, so that the first capacitor stores a voltage of the gate of the current output transistor; and the current output transistor is configured to output a current corresponding to the data signal voltage of its gate;   the control circuit comprises a first transistor, a second transistor and one second capacitor;   a gate of the first transistor is connected to an input terminal of a reset control signal, a first terminal of the first transistor is connected to the voltage circuit, a second terminal of the first transistor is connected to a first terminal of the second capacitor and a first terminal of the second transistor, a gate of the second transistor is connected to an input terminal of a reverse reset control signal, and a second terminal of the second transistor is connected to the gate of the current output transistor; and   the compensation control circuit comprises a third transistor and a fourth transistor; and a gate of the third transistor is connected to an input terminal of a first control signal, a first terminal of the third transistor is connected to an input terminal of an initialization voltage, a second terminal of the third transistor, a first terminal of the fourth transistor, and the first terminal of the first capacitor are all directly connected to the gate of the current output transistor, a gate of the fourth transistor is connected to an input terminal of a second control signal, and a second terminal of the fourth transistor is connected to the first terminal of the current output transistor.   
     
     
         2 - 3 . (canceled) 
     
     
         4 . The circuit according to  claim 1 , wherein a capacitance of the first capacitor is greater than a capacitance of the second capacitor. 
     
     
         5 . The circuit according to  claim 1 , further comprising a potential clamping transistor and a voltage divider capacitor, wherein the second terminal of the second transistor is connected to the gate of the current output transistor through the voltage divider capacitor; and
 a gate of the potential clamping transistor is connected to the input terminal of a reset control signal, a first terminal of the potential clamping transistor is connected to a first potential input terminal, a second terminal of the potential clamping transistor is connected to the second terminal of the second transistor and a first terminal of the voltage divider capacitor, and a second terminal of the voltage divider capacitor is connected to the gate of the current output transistor.   
     
     
         6 . The circuit according to  claim 1 , wherein the voltage circuit comprises a plurality of dual-channel selectors, a first input terminal of each dual-channel selector is connected to a first level output terminal, a second input terminal of each dual-channel selector is connected to a second level output terminal, and an output terminal of each dual-channel selector is connected to an input terminal of the control circuit. 
     
     
         7 . The circuit according to  claim 6 , wherein a first level output by the first level output terminal and a second level output by the second level output terminal are adjacent gamma voltages. 
     
     
         8 . The circuit according to  claim 6 , wherein the control circuit comprises a plurality of first switches, a plurality of second capacitors, and a plurality of second switches; and
 first terminals of the plurality of first switches are respectively connected to the output terminals of the dual-channel selectors, second terminals of the plurality of first switches are respectively connected to first terminals of the plurality of second switches, second terminals of the plurality of second switches are all connected to the gate of the current output transistor, and first terminals of the plurality of second capacitors are respectively connected to the second terminals of the plurality of first switches.   
     
     
         9 . The circuit according to  claim 8 , further comprising a third switch and a voltage divider capacitor, wherein the second terminals of the plurality of second switches are all connected to the gate of the current output transistor through the voltage divider capacitor; and
 a first terminal of the third switch is connected to a first potential input terminal, and a second terminal of the third switch is connected to the second terminal of the second switch and a first terminal of the voltage divider capacitor.   
     
     
         10 . A display panel, comprising:
 a display area and a non-display area, wherein the display area is provided with a plurality of pixel circuits, and the non-display area is provided with the circuit according to  claim 1 ; the pixel circuits are connected to the circuit through data lines and switch circuits; and the circuit provides data signal currents for the pixel circuits through the data lines and the switch circuits; and   a fifth transistor, wherein the switch circuit comprises a switch transistor; wherein   a gate of the fifth transistor is connected to an input terminal of a reset control signal, a first terminal of the fifth transistor is connected to a first input terminal of a reference voltage of the pixel circuit, and a second terminal of the fifth transistor is connected to an input terminal of a data signal current of the pixel circuit; and a gate of the switch transistor is connected to an input terminal of a switch control signal of the pixel circuit, a first terminal of the switch transistor is connected to a first terminal of a current conversion transistor of the circuit, and a second terminal of the switch transistor is connected to the input terminal of a data signal current of the pixel circuit;   the pixel circuit comprises a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a third capacitor, and a light-emitting device; and   a first terminal of the sixth transistor and a first terminal of the seventh transistor are connected to the input terminal of a data signal current of the pixel circuit, a second terminal of the sixth transistor is connected to a gate of the eighth transistor and a first terminal of the third capacitor, a gate of the sixth transistor and a gate of the seventh transistor are connected to an input terminal of a scanning signal of the pixel circuit, a second terminal of the seventh transistor is connected to a second terminal of the eighth transistor, and a first terminal of the eighth transistor is connected to a first input terminal of a power signal of the pixel circuit; and a second terminal of the third capacitor is connected to a second input terminal of a reference voltage of the pixel circuit, the second terminal of the eighth transistor is connected to a first terminal of the ninth transistor, a gate of the ninth transistor is connected to an input terminal of a light-emitting control signal of the pixel circuit, a second terminal of the ninth transistor is connected to an anode of the light-emitting device, and a cathode of the light-emitting device is connected to a second input terminal of a power signal of the pixel circuit.