Selective pixel output
Abstract
In one embodiment, a computing system may write pixel values into a buffer in a tile order. Each writing operation may write a block of pixel values into two memory units. The first memory unit may receive a first half of the block of pixel values. The second memory unit may receive a second half of the block of the pixel values. The system may read a subset of pixel values from the buffer in a pixel row order. Each reading operation may read a second block of pixel values from the two memory units of the buffer. The first memory unit may provide a first half of the second block of pixel values. The second memory unit may provide a second half of the second block of pixel values. The system may output the subset of pixel values read from the buffer via an output data bus.
Claims
exact text as granted — not AI-modified1 - 20 . (canceled)
21 . A method comprising, by a computing system:
writing a plurality of pixel values into a first buffer in a tile order using multiple writing operations, wherein the first buffer comprises at least two memory units, and wherein each writing operation writes a first block of pixel values associated with multiple pixel rows of a tile into the two memory units of the first buffer, with a first memory unit of the two memory units receiving a first half of the first block of pixel values associated with a first pixel row of the tile and a second memory unit of the two memory units receiving a second half of the first block of the pixel values associated with a second pixel row of the tile; reading a subset of pixel values of the plurality of pixel values from the first buffer in a pixel row order using multiple reading operations, wherein each reading operation reads a second block of pixel values associated with a pixel row across multiple tiles from the two memory units of the first buffer, with the first memory unit of the two memory units providing a first half of the second block of pixel values associated with a first tile of the multiple tiles and the second memory unit of the two memory units providing a second half of the second block of pixel values associated with a second tile of the multiple tiles; and outputting the subset of pixel values of the plurality of pixel values read from the first buffer via an output data bus.
22 . The method of claim 21 , wherein the plurality of pixel values are organized into a plurality of tiles, further comprising:
determining a tile validity indicator for each tile of the plurality of tiles, wherein the tile validity indicator indicates whether that tile is a valid tile that is associated foreground display contents.
23 . The method of claim 22 , wherein the subset pixel values of the plurality of pixel values are read from the first buffer based on a determination that the tile validity indicators indicate that the subset of pixel values are associated with valid tiles that are associated with one or more foreground display contents.
24 . The method of claim 22 , wherein the subset of pixel values have a smaller data size than the plurality of pixel values when the tile validity indicators indicate one or more tiles of the plurality of tiles are invalid tiles that are associated with background areas of a target image.
25 . The method of claim 24 , wherein the first buffer is used for buffering image data between a display engine and a display connected with the output data bus, wherein the output data bus has a limited bandwidth, and wherein the smaller data size of the subset of pixel values allows the subset of pixel values to be transmitted via the output data bus with the limited bandwidth.
26 . The method of claim 21 , wherein the first buffer and a second buffer collectively works as a double-buffered pixel buffer, and wherein the first buffer and the second buffer are accessed concurrently.
27 . The method of claim 26 , wherein the subset of pixel values are read from the first buffer while a plurality of subsequent pixel values are written into the second buffer concurrently.
28 . The method of claim 26 , wherein the plurality of pixel values are written into the first buffer while a subset of proceeding pixel values are read from the second buffer concurrently.
29 . The method of claim 21 , wherein the first block of pixel values correspond to a 4×2 array of pixel values associated with two pixel rows, and wherein the second block of pixel values correspond to an 8×1 array of pixel values across two tiles.
30 . The method of claim 21 , further comprising:
receiving, by a second computing system of a display and via the output data bus, the subset of pixel values and a plurality of tile validity indicators associated with respective tiles of the plurality of pixel values; determining, by the second computing system of the display, a display position for each pixel value of the subset of pixel values based on at least on one or more tile validity indicators associated with one or more tiles that are prior to a valid tile associated with that pixel value; and outputting the subset of pixel values to the display based on the determined display positions for the subset of pixel values.
31 . The method of claim 30 , wherein the display position for that pixel value is determined based on a number of the one or more tiles that are prior to the valid tile of that pixel value.
32 . The method of claim 30 , wherein the display position for that pixel value is determined based on a relative position of a corresponding pixel within the valid title associated with that pixel value.
33 . The method of claim 30 , wherein the display displays one or more foreground display contents as represented by the subset of pixel values, wherein the one or more foreground display contents correspond to one or more artificial reality objects, and wherein the display has one or more unlit areas corresponding to one or more background areas of a target image.
34 . The method of claim 33 , wherein the one or more foreground display contents are associated with one or more valid tiles, and wherein the one or more background areas are associated with one or more invalid tiles.
35 . One or more computer-readable non-transitory storage media embodying software that is operable when executed to:
write a plurality of pixel values into a first buffer in a tile order using multiple writing operations, wherein the first buffer corresponds to at least two memory units, and wherein each writing operation writes a first block of pixel values associated with multiple pixel rows of a tile into the two memory units of the first buffer, with a first memory unit of the two memory units receiving a first half of the first block of pixel values associated with a first pixel row of the tile and a second memory unit of the two memory units receiving a second half of the first block of the pixel values associated with a second pixel row of the tile; read a subset of pixel values of the plurality of pixel values from the first buffer in a pixel row order using multiple reading operations, wherein each reading operation reads a second block of pixel values associated with a pixel row across multiple tiles from the two memory units of the first buffer, with the first memory unit of the two memory units providing a first half of the second block of pixel values associated with a first tile of the multiple tiles and the second memory unit of the two memory units providing a second half of the second block of pixel values associated with a second tile of the multiple tiles; and output the subset of pixel values of the plurality of pixel values read from the first buffer via an output data bus.
36 . The media of claim 35 , wherein the plurality of pixel values are organized into a plurality of tiles, and wherein the media further embodies software that is operable when executed to:
determine a tile validity indicator for each tile of the plurality of tiles, wherein the tile validity indicator indicates whether that tile is a valid tile that is associated foreground display contents.
37 . The media of claim 36 , wherein the subset pixel values of the plurality of pixel values are read from the first buffer based on a determination that the tile validity indicators indicate that the subset of pixel values are associated with tiles that are associated with at least one foreground display content.
38 . A system comprising:
one or more processors; and one or more computer-readable non-transitory storage media coupled to one or more of the processors and comprising instructions operable when executed by one or more of the processors to cause the system to:
write a plurality of pixel values into a first buffer in a tile order using multiple writing operations, wherein the first buffer corresponds to at least two memory units, and wherein each writing operation writes a first block of pixel values associated with multiple pixel rows of a tile into the two memory units of the first buffer, with a first memory unit of the two memory units receiving a first half of the first block of pixel values associated with a first pixel row of the tile and a second memory unit of the two memory units receiving a second half of the first block of the pixel values associated with a second pixel row of the tile;
read a subset of pixel values of the plurality of pixel values from the first buffer in a pixel row order using multiple reading operations, wherein each reading operation reads a second block of pixel values associated with a pixel row across multiple tiles from the two memory units of the first buffer, with the first memory unit of the two memory units providing a first half of the second block of pixel values associated with a first tile of the multiple tiles and the second memory unit of the two memory units providing a second half of the second block of pixel values associated with a second tile of the multiple tiles; and
output the subset of pixel values of the plurality of pixel values read from the first buffer via an output data bus.
39 . The system of claim 38 , wherein the plurality of pixel values are organized into a plurality of tiles, and wherein the system is further configured to:
determine a tile validity indicator for each tile of the plurality of tiles, wherein the tile validity indicator indicates whether that tile is a valid tile that is associated foreground display contents.
40 . The system of claim 39 , wherein the subset pixel values of the plurality of pixel values are read from the first buffer based on a determination that the tile validity indicators indicate that the subset of pixel values are associated with tiles that are associated with at least one foreground display content.Join the waitlist — get patent alerts
Track US2021375361A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.