Method of manufacturing a three-dimensional non-volatile memory device

Abstract

22In a method of manufacturing a non-volatile memory device, insulating layers and conductive gates may be alternately formed on a semiconductor substrate to form a stack structure. A contact hole may be formed through the stack structure. A channel layer may be formed on a surface of the contact hole. The contact hole may be filled with a gap-fill insulating layer. The gap-fill insulating layer may be etched by a target depth to define a preliminary junction region. The channel layer may be etched until a surface of the channel layer may correspond to a surface of an uppermost gate among the gates. Diffusion-preventing ions may be implanted into the channel layer. A capping layer with impurities may be formed in the preliminary junction region.

What is claimed is: 
     
         1 . A semiconductor memory device having a plurality of cell strings, the memory device comprising:
 a stack of a plurality of alternating insulating layers and gates; and   a plurality of channel pillars penetrating through the stack in a spaced apart arrangement,   wherein each of the plurality of channel pillars includes:   a memory layer formed conformally inside an internal surface of each of a plurality of holes formed in the stack;   a channel layer formed conformally on each of the plurality of memory layers; and   a drain region formed in an upper region of each hole,   wherein a bottom surface of the drain region includes a first portion and a second portion surrounding the first portion, a bottom surface of the second portion extends more than a bottom surface of the first region by a predetermined length, and the bottom surface of the second portion corresponds to an upper surface of an uppermost gate of the stack.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein the each of the plurality of cell strings includes a source selection transistor, a plurality of memory cell transistors and a drain selection transistor which are connected in series,
 wherein the uppermost gate is corresponded to a gate of the drain selection transistor.   
     
     
         3 . The semiconductor memory device of  claim 1 , further comprising a gap-fill insulating layer formed on the channel layer to fill each hole. 
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the bottom surface of the first portion is contacted to an upper surface of the gap-fill insulating layer. 
     
     
         5 . The semiconductor memory device of  claim 3 , wherein an upper surface of the gap-fill insulating layer is positioned between an upper surface of the memory layer and an upper surface of the channel layer, and the upper surface of the channel layer is formed not to be lower than the upper surface of the uppermost gate. 
     
     
         6 . The semiconductor memory device of  claim 1 , wherein a sidewall of the drain region is contacted to the memory layer. 
     
     
         7 . The semiconductor memory device of  claim 1 , wherein the drain region includes a polysilicon with conductive impurities.