US2021376535A1PendingUtilityA1

Capacitor in socket

65
Assignee: R&D CIRCUITS INCPriority: May 29, 2020Filed: May 29, 2020Published: Dec 2, 2021
Est. expiryMay 29, 2040(~13.9 yrs left)· nominal 20-yr term from priority
G01R 1/06772G01R 1/045G01R 1/07342H01R 13/6625H01R 13/17G01R 1/0483
65
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Claims

Abstract

The present invention provides for an improved method and structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN) by placing capacitors on the top of the pin array on the printed circuit board (PCB) of the structure to decouple the PDN and results in lower impedance benefitting the frequency range of the PDN effecting a significant performance improvement in the spring-pin inductance from the transmission line. This reduction in impedance reduces the power supply ripple.

Claims

exact text as granted — not AI-modified
What is claimed: 
     
         1 . A structure for forming an electrical interconnects mechanism in a Power Distribution Network (PDN), comprising:
 capacitors placed on top of one or more pin arrays in one or more respective sockets on top of a printed circuit board (PCB) of the PDN to decouple the PDN and resulting in lowering impedance to benefit frequency range of the PDN to effect a performance improvement in spring-pin inductance from a transmission line thereby reducing a power supply ripple.   
     
     
         2 . The structure according to  claim 1  further comprising
 one or more a plated inner holes or vias for one or more pins that touches or makes contact with said plated inner one or more spring pins in said PCB as it is held in place wherein a top narrow plunger-like electrical connection is made by said one or more pins for a fine pitch solution of approximately 0.4 mm and 0.35 mm pitch sockets. 
 
     
     
         3 . The structure according to  claim 1  wherein said holes or vias have room for hole to copper tolerances of 2.5 mils to 5 mils to allow for a minimum copper width of no less than approximately 1.8 mils in between copper located between said holes and said vias wherein said hole to copper tolerances is a distance between a via or non-plated through hole and a copper feature on a PCB. 
     
     
         4 . The method of building holes or vias having room to accommodate said power and ground planes according to  claim 3  comprising:
 etching power or ground planes at one or more top surfaces of one or more respective sockets; 
 drilling a drilled one or more respective stepped holes; 
 plating one or more respective holes; 
 removing top copper material on each of said power or ground planes; 
 routing in said power or ground planes; and 
 adding spring pins in said power or ground planes.

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