Semiconductor memory device and semiconductor device

Abstract

A semiconductor memory device includes: a substrate including a cell region and a connection region; a first word line stack comprising a plurality of first word lines that extend to the connection region and are stacked on the cell region,; a second word line stack comprising a plurality of second word lines that extend to the connection region and are stacked on the cell region, the second word line being adjacent to the first word line stack; vertical channels in the cell region of the substrate, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; a bridge region that connects the first word lines of the first word line stack with the second word lines of the second word line stack; and a local planarized region under the bridge region.

1 . A semiconductor memory device comprising:
 a substrate including a cell region and a connection region;   a first word line stack including a first ground selection line, a plurality of first word lines on the first ground selection line, and a first string selection line on the plurality of first word lines, the plurality of first word lines extending to the connection region:   a second word line stack including a second ground selection line, a plurality of second word lines on the second ground selection line, and a second string selection line on the plurality of second word lines, the plurality of second word lines extending to the connection region:   vertical channels in the cell region, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines; and   bit lines connecting the vertical channels,   wherein the first ground selection line and the second ground selection line are connected via a local planarized region.   
     
     
         2 . The semiconductor memory device of  claim 1 , wherein each of the first ground selection line and the second ground selection line has a recess that is laterally recessed on a side thereof near the local planarized region. 
     
     
         3 . The semiconductor memory device of  claim 1 , wherein the local planarized region between the first ground selection line and the second ground selection line is at least partially filled by a protruding portion of the substrate. 
     
     
         4 . The semiconductor memory device of  claim 3 , wherein the protruding portion is at a higher level than an upper surface of the substrate under the first word line stack. 
     
     
         5 . The semiconductor memory device of  claim 1 , wherein the local planarized region between the first ground selection line and the second ground selection line is at least partially filled by a filler of an insulating layer. 
     
     
         6 . The semiconductor memory device of  claim 1 , wherein each of the plurality of first word lines is connected to corresponding one of the plurality of second word lines at the same level via a bridge region. 
     
     
         7 . The semiconductor memory device of  claim 6 , wherein the bridge region is above the local planarized region. 
     
     
         8 . The semiconductor memory device of  claim 1 , wherein each of the first ground selection line and the second ground selection line has a protruding portion on a side thereof and the protruding portion extends toward the local planarized region. 
     
     
         9 . The semiconductor memory device of  claim 1 , wherein the local planarized region is in the connection region. 
     
     
         10 . A semiconductor memory device comprising:
 a substrate including a cell region and a connection region;   a first word line stack including a first ground selection line, a plurality of first word lines on the first ground selection line, and a first string selection line on the plurality of first word lines, the plurality of first word lines extending to the connection region;   a second word line stack including a second ground selection line, a plurality of second word lines on the second ground selection line, and a second string selection line on the plurality of second word lines, the plurality of second word lines extending to the connection region;   vertical channels in the cell region, the vertical channels being connected to the substrate and coupled with the plurality of first and second word lines;   a dielectric film between the substrate and the first ground selection line and between the substrate and the second ground selection line;   bit lines connecting the vertical channels; and   a local planarized region in the connection region between the first ground selection line and the second ground selection line,   wherein a side surface of the first ground selection line facing the local planarized region is coplanar with a side surface of the dielectric film facing the local planarized region.   
     
     
         11 . The semiconductor memory device of  claim 10 , wherein a width of the local planarized region in a direction traversing the first ground selection line and the second ground selection line at a right angle is greater than a distance between the first ground selection line and the second ground selection line. 
     
     
         12 . The semiconductor memory device of  claim 11 , wherein each of the first ground selection line and the second ground selection line has a recess that is laterally recessed on a side thereof adjacent to the local planarized region. 
     
     
         13 . The semiconductor memory device of  claim 10 , wherein a width of the local planarized region in a direction traversing the first ground selection line and the second ground selection line at a right angle is smaller than a distance between the first ground selection line and the second ground selection line. 
     
     
         14 . The semiconductor memory device of  claim 13 , wherein each of the first ground selection line and the second ground selection line has a protruding portion on a side thereof and the protruding portion extends toward the local planarized region. 
     
     
         15 . The semiconductor memory device of  claim 10 , wherein the local planarized region between the first ground selection line and the second ground selection line is at least partially filled by a protruding portion of the substrate. 
     
     
         16 . The semiconductor memory device of  claim 15 , wherein the protruding portion of the substrate in the local planarized region is higher than an upper surface of the substrate under the first word line stack by about 20 Å to about 300 Å. 
     
     
         17 . The semiconductor memory device of  claim 15 , wherein a protrusion height at the protruding portion of the substrate in the local planarized region is about 40% to about 140% of the total height of the first ground selection line and the dielectric film. 
     
     
         18 . A semiconductor memory device comprising:
 a substrate including a cell region and a connection region;   a first word line stack including a first ground selection line, a plurality of first word lines on the first ground selection line, and a first string selection line on the plurality of word lines, the plurality of first word lines extending to the connection region;   a second word line stack including a second ground selection line, a plurality of second word lines on the second ground selection line, and a second string selection line on the plurality of second word lines, the plurality of second word lines extending to the connection region;   a third word line stack including a third ground selection line, a plurality of third word lines on the third ground selection line, and a third string selection line on the plurality of third word lines, the plurality of third word lines extending to the connection region;   vertical channels in the cell region, the vertical channels being connected to the substrate and coupled with the plurality of first, second and third word lines;   bit lines connecting the vertical channels;   a first local planarized region in the connection region between the first ground selection line and the second ground selection line; and   a second local planarized region in the connection region between the second ground selection line and the third ground selection line.   
     
     
         19 . The semiconductor memory device of  claim 18 , wherein each of the first and the second local planarized region includes an oxide layer formed by oxidizing a part of the substrate, and the oxide layer of the substrate has a shape with a thickness that gradually reduces towards edge regions of the first and/or the second local planarized region. 
     
     
         20 . The semiconductor memory device of  claim 19 , wherein upper surfaces of the first ground selection line, the second ground selection line, or the third ground selection line near the first and/or the second local planarized region gradually rise towards the first and/or the second local planarized region.