Methods of fabricating single-stack bipolar-based esd protection devices

Abstract

Methods of fabricating ESD protection devices include forming a single-stage voltage clamp device with high holding voltage characteristics (e.g., ˜40 V) includes two p-n-p structures coupled in series via an n-p-n structure. The device has a low-voltage terminal that may be coupled to the ground of a circuit and high voltage terminal that may be coupled to a voltage source of the circuit. A highly-doped floating (n+)/(p+) junction region within a heavily doped base of the low-voltage-side p-n-p structure allows for holding voltages of at least 40 V in the single-stage device without the need to employ two such devices in series to achieve the desired holding voltage.

What is claimed is: 
     
         1 . A method of forming a semiconductor device, comprising:
 forming a first region of semiconductor material having a first conductivity type;   forming a second region of semiconductor material partially overlapping the first region, the second region having a first conductivity type;   forming a third region of semiconductor material within the first region, the third region having a second conductivity type opposite the first conductivity type;   forming a fourth region of semiconductor material having the second conductivity type;   forming a fifth region of semiconductor material having the first conductivity type;   forming a sixth region of semiconductor material within the first region, the sixth region having the second conductivity type; and   forming a seventh region of semiconductor material within the first region, the seventh region having the first conductivity type;   wherein:
 a portion of the first region is disposed between the third region and the second region; 
 the second region is disposed between the first region and the fourth region; 
 the first region has a dopant concentration that is greater than the second region; 
 the fifth region and the third region are electrically connected; 
 the sixth region and the seventh region are abutting and electrically connected, and disposed between the third region and the second region; and 
 the sixth region and the seventh region are floating. 
   
     
     
         2 . The method of  claim 1 , wherein:
 the first region comprises a first base well region;   the second region comprises a triggering base well region;   the third region comprises an emitter region;   the fourth region comprises a collector region; and   the fifth region comprises a base contact region.   
     
     
         3 . The method of  claim 1 , wherein:
 the first region has a dopant concentration that is greater than or equal to 1e16, and   the second region has a dopant concentration that is less than or equal to 1e19.   
     
     
         4 . The method of  claim 1 , wherein the second region and the fourth region are spaced apart by a distance. 
     
     
         5 . The method of  claim 1 , further comprising:
 forming an eighth region of semiconductor material having the first conductivity type, the eighth region underlying the first region and the second region, and overlying a buried region of semiconductor material having the second conductivity type;   wherein the eighth region has a dopant concentration that is less than the first region and the second region.   
     
     
         6 . The method of  claim 5 , wherein the buried region has an outer region and an inner region which are heavily doped regions of the second conductivity type, the inner region being surrounded by a ring region which is an undoped or lightly doped ring shaped region and which is surrounded by the outer region. 
     
     
         7 . The method of  claim 5 , wherein a portion of the eighth region is disposed between the second region and the fourth region. 
     
     
         8 . The method of  claim 1 , wherein the sixth region and the seventh region are short-circuited together. 
     
     
         9 . The method of  claim 1 , wherein the second region and the fourth region are short-circuited together. 
     
     
         10 . A method of forming a protection device structure, comprising:
 forming a first base well region of semiconductor material having a first conductivity type, wherein the first base well region includes a first region and a second region, the first region having a higher dopant concentration than the second region, and the second region is disposed between the first region and a collector region of semiconductor material having the second conductivity type;   forming a first emitter region of semiconductor material within the first region of the first base well region, the first emitter region having a second conductivity type opposite the first conductivity type, wherein at least a portion of the first region of the first base well region is disposed between the first emitter region and the second region of the first base well region;   forming a first base contact region of semiconductor material within the first region of the first base well region, the first base contact region having the first conductivity type, wherein at least a portion of the first region of the first base well region is disposed between the first base contact region and the first emitter region, and the first emitter region is disposed between the first base contact region and the second region of the first base well region, and the first emitter region and the first base contact region are electrically connected;   forming a first floating region of semiconductor material within the first region of the first base well region, the first floating region having the second conductivity type, wherein the first floating region is disposed between the first emitter region and the second region of the first base well region; and   forming a second floating region of semiconductor material within the first region of the first base well region, the second floating region having the first conductivity type, wherein the second floating region is disposed between the first floating region and the second region of the first base well region, and the first floating region and the second floating region are electrically connected;   forming a second base well region of semiconductor material having the first conductivity type, the collector region being disposed between the second region of the first base well region and the second base well region;   forming a second emitter region of semiconductor material within the second base well region, the second emitter region having the second conductivity type; and   forming a second base contact region of semiconductor material within the second base well region, the second base contact region having the first conductivity type, wherein the second base contact region and the second emitter region are electrically connected;   wherein:   at least a portion of the second base well region is disposed between the second base contact region and the second emitter region; and   the second emitter region is disposed between the second base contact region and the collector region.   
     
     
         11 . The method of  claim 10 , wherein the second region of the first base well region is spaced apart from the collector region. 
     
     
         12 . The method of  claim 10 , further comprising:
 forming a buried region of semiconductor material having the second conductivity type; and   forming a doped region of semiconductor material having the first conductivity type overlying and abutting the buried region;   wherein:
 the doped region underlies and abuts the first base well region and the second base well region; 
 the doped region has a dopant concentration less than the first base well region; and 
 the buried region underlies the second base well region and abuts the collector region. 
   
     
     
         13 . The method of  claim 12 , wherein the buried region has an outer region and an inner region which are heavily doped regions of the second conductivity type;
 the inner region being surrounded by a ring region which is an undoped or lightly doped ring-shaped region and which is surrounded by the outer region; and   the inner region of the buried region underlies the first base well region and the outer region of the buried region underlies the second base well region.   
     
     
         14 . The method of  claim 12 , wherein a portion of the doped region is disposed between the second region of the first base well region and the collector region. 
     
     
         15 . The method of  claim 10 , the device further comprising:
 coupling a first interface terminal coupled to the second base contact region;   coupling a second interface terminal coupled to the first base contact region; and   coupling functional circuitry to the first interface terminal and the second interface terminal.   
     
     
         16 . The method of  claim 10 , wherein the first floating region and the second floating region are abutting. 
     
     
         17 . A method of fabricating a protection device structure on a semiconductor substrate, the method comprising:
 forming a well region of semiconductor material in the semiconductor substrate, the well region having a first conductivity type;   forming a first portion of the well region as a higher dopant concentration than a second portion of the well region, wherein the second portion of the base well region is disposed between the first portion of the base well region and a collector region of semiconductor material having the second conductivity type;   forming an emitter region of semiconductor material within the first portion of the base well region, the emitter region having a second conductivity type opposite the first conductivity type, wherein at least a portion of the first portion of the base well region is disposed between the emitter region and the second portion of the base well region;   forming a base contact region of semiconductor material in the semiconductor substrate, the base contact region having a first conductivity type;   forming a first floating region of semiconductor material within the first portion of the base well region between the emitter region and the second portion of the base well region, the first floating region having the second conductivity type;   forming a second floating region of semiconductor material within the first portion of the base well region between the emitter region and the second portion of the base well region, the second floating region having the first conductivity type, wherein the first floating region and the second floating region are electrically connected; and   providing an electrical connection between the base contact region and the emitter region.   
     
     
         18 . The method of  claim 17 , wherein the base well region is formed within a doped region of semiconductor material having the second conductivity type, and wherein a portion of the doped region is disposed between the second portion of the base well region and the collector region, and the doped region has a dopant concentration lower than the second portion of the base well region.