Method for fabricating a metal-oxide-semiconductor transistor

Abstract

A semiconductor substrate having a gate dielectric layer and a conductive layer is provided. The conductive layer is patterned into a main gate portion. A drain region and a source region are formed on two sides of the main gate portion, respectively. By thinning down the gate dielectric layer after patterning the conductive layer into the main gate portion, a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between a channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region are formed. A first extension gate portion and a second extension gate portion are formed on two opposite sidewalls of the main gate portion, respectively. The main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor.

What is claimed is: 
     
         1 . A method for fabricating a metal-oxide-semiconductor (MOS) transistor, comprising:
 providing a semiconductor substrate having thereon a gate dielectric layer and a first conductive layer;   patterning the conductive layer into a main gate portion;   performing an ion implantation process to form a drain region and a source region in the semiconductor substrate on two sides of the main gate portion, respectively, wherein a channel region is between the drain region and the source region;   thinning down the gate dielectric layer after patterning the conductive layer into the main gate portion, thereby forming a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between the channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region, wherein the first portion and the third portion are thinner than the second portion; and   forming a first extension gate portion and a second extension gate portion on two opposite sidewalls of the main gate portion, respectively, wherein the main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor.   
     
     
         2 . The method for fabricating a MOS transistor according to  claim 1  further comprising:
 forming a first dielectric spacer and a second dielectric spacer on the first extension gate portion and the second extension gate portion, respectively. 
 
     
     
         3 . The method for fabricating a MOS transistor according to  claim 2 , wherein the first dielectric spacer and the second dielectric spacer are situated directly on the first portion and the third portion of the gate dielectric layer, respectively. 
     
     
         4 . The method for fabricating a MOS transistor according to  claim 2  further comprising:
 forming a first salicide layer on the drain region and a second salicide layer on the source region. 
 
     
     
         5 . The method for fabricating a MOS transistor according to  claim 1 , wherein the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer. 
     
     
         6 . The method for fabricating a MOS transistor according to  claim 5 , wherein the first extension gate portion of the gate electrode is in direct contact with the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is in direct contact with the third portion of the gate dielectric layer. 
     
     
         7 . The method for fabricating a MOS transistor according to  claim 1 , wherein a first vertical PN junction, which is between the drain region and the channel region and is proximate to a top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode. 
     
     
         8 . The method for fabricating a MOS transistor according to  claim 7 , wherein a second vertical PN junction, which is between the source region and the channel region and is proximate to the top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode. 
     
     
         9 . The method for fabricating a MOS transistor according to  claim 1 , wherein the MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage. 
     
     
         10 . A method for fabricating a metal-oxide-semiconductor (MOS) transistor, comprising:
 providing a semiconductor substrate;   forming a drain region, a source region in the semiconductor substrate, and a channel region between the drain region and the source region;   forming a gate electrode on the channel region, wherein the gate electrode comprises a main gate portion directly above the channel region, and an extension gate portion on a sidewall of the main gate portion;   forming a gate dielectric layer having different thicknesses between the gate electrode and the semiconductor substrate, wherein the extension gate portion of the gate electrode is situated directly on a thinner portion of the gate dielectric layer and the main gate portion of the gate electrode is situated directly on a thicker portion of the gate dielectric layer; and   forming a dielectric spacer covering the extension gate portion of the gate electrode, wherein the dielectric spacer is situated directly on the thinner portion of the gate dielectric layer.   
     
     
         11 . The method according to  claim 10 , wherein a first portion of the gate dielectric layer that is situated directly between the drain region and the gate electrode is thinner than a second portion of the gate dielectric layer that is situated directly between the channel region and the gate electrode. 
     
     
         12 . The method according to  claim 11 , wherein a third portion of the gate dielectric layer that is situated directly between the source region and the gate electrode is thinner than the second portion of the gate dielectric layer that is situated directly between the channel region and the gate electrode. 
     
     
         13 . The method according to  claim 12 , wherein the gate electrode comprises a main gate portion disposed directly above the channel region, and a first extension gate portion and a second extension gate portion disposed on two opposite sidewalls of the main gate portion, respectively. 
     
     
         14 . The method according to  claim 13 , wherein the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer. 
     
     
         15 . The method according to  claim 14 , wherein the first extension gate portion of the gate electrode is in direct contact with the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is in direct contact with the third portion of the gate dielectric layer. 
     
     
         16 . The method according to  claim 13 , wherein the main gate portion, the first extension gate portion and the second extension gate portion of the gate electrode are composed of doped polysilicon, silicide, or metal. 
     
     
         17 . The method according to  claim 13 , wherein the first extension gate portion of the gate electrode is covered with a first dielectric spacer and the second extension gate portion of the gate electrode is covered with a second dielectric spacer. 
     
     
         18 . The method according to  claim 13 , wherein a first vertical PN junction, which is between the drain region and the channel region and is proximate to a top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode. 
     
     
         19 . The method according to  claim 18 , wherein a second vertical PN junction, which is between the source region and the channel region and is proximate to the top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.