Current generation device

Abstract

In an embodiment, a device for generating a first current from a second current, comprises: an output transistor configured to generate the first current; a first circuit configured to generate a third current representative of the second current and to draw it from a first node; a second circuit configured to generate a fourth current representative of the first current and to supply it to the first node; and a third circuit receiving a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw it from a control terminal of the output transistor.

What is claimed is: 
     
         1 . A circuit comprising:
 an input terminal;   an output terminal;   a first current mirror having a first branch coupled to the input terminal and a second branch coupled to the output terminal;   a second current mirror having a first branch coupled to the first branch of the first current mirror and a second branch coupled to an intermediate node;   a third current mirror having a first branch coupled to the intermediate node;   a fourth current mirror having a first branch coupled to the intermediate node, and a second branch coupled to the output terminal; and   a first transistor having a current path coupled to a second branch of the third current mirror and a control terminal coupled to the output terminal.   
     
     
         2 . The circuit of  claim 1 , wherein the second branch of the fourth current mirror is directly connected to the second branch of the first current mirror. 
     
     
         3 . The circuit of  claim 1 , further comprising a current source configured to provide an input current to the input terminal. 
     
     
         4 . The circuit of  claim 1 , further comprising an output transistor having a control terminal coupled to the output terminal. 
     
     
         5 . The circuit of  claim 4 , wherein the input terminal is configured to receive a first current that is 25 times smaller or less than an output current flowing through a current path of the output transistor. 
     
     
         6 . The circuit of  claim 4 , wherein the first branch of the fourth current mirror comprises a second transistor, wherein the second branch of the fourth current mirror comprises a third transistor, wherein the second transistor has a W/L ratio equal to k times a W/L ratio of the third transistor, wherein the first current mirror comprises a fourth transistor, wherein the output transistor has a W/L ratio equal to N times a W/L ratio of the fourth transistor, wherein k is greater or equal to 10, and wherein N is greater than 25. 
     
     
         7 . The circuit of  claim 6 , wherein k is lower than 20. 
     
     
         8 . The circuit of  claim 6 , wherein N is greater than 50. 
     
     
         9 . The circuit of  claim 1 , further comprising first and second voltage rails, wherein the second branch of the first current mirror comprises a second transistor having a current path coupled between the first voltage rail and the output terminal, and wherein the second branch of the fourth current mirror comprises a third transistor having a current path coupled between the output terminal and the second voltage rail. 
     
     
         10 . The circuit of  claim 9 , further comprising an output transistor having a control terminal coupled to the output terminal and a current path coupled to the second voltage rail. 
     
     
         11 . The circuit of  claim 10 , wherein a first current path terminal of the output transistor is directly connected to the second voltage rail, and wherein a second current path terminal of the output transistor is directly connected to a control terminal of a further transistor. 
     
     
         12 . The circuit of  claim 1 , further comprising first and second voltage rails, wherein the second branch of the second current mirror comprises a second transistor having a current path coupled between the second voltage rail and the intermediate node, and wherein the first branch of the third current mirror comprises a third transistor having a current path coupled between the intermediate node and the first voltage rail. 
     
     
         13 . The circuit of  claim 1 , wherein transistors of the first, second, and fourth current mirrors are of the N-type, and wherein transistors of the third current mirror are of the P-type. 
     
     
         14 . The circuit of  claim 1 , wherein the input terminal is configured to receive a first current, wherein the second branch of the second current mirror is configured to draw a second current from the intermediate node, wherein the intermediate node is configured to receive a third current from the first branch of the third current mirror, wherein a variation of the first current is configured to cause a corresponding variation of the second and third currents so that the variation of the second current is faster than the variation of the third current. 
     
     
         15 . A circuit comprising:
 an input terminal;   an output terminal;   a first transistor having a first current path terminal coupled to the input terminal and a control terminal coupled to the first current path terminal of the first transistor;   a second transistor having a first current path terminal coupled to the output terminal and a control terminal coupled to the control terminal of the first transistor;   a third transistor having a first current path terminal coupled to a second current path terminal of the first transistor, and a control terminal coupled to the first current path terminal of the third transistor;   a fourth transistor having a first current path terminal coupled to a second current path terminal of the third transistor, a control terminal coupled to the control terminal of the third transistor, and a second current path terminal coupled to an intermediate node;   a fifth transistor having a first current path terminal coupled to the intermediate node;   a sixth transistor having a control terminal coupled to a control terminal of the fifth transistor, a first current path terminal coupled to the control terminal of the fifth transistor, and a second current path terminal coupled to a second current path terminal of the fifth transistor;   a seventh transistor having a first current path terminal coupled to the first current path terminal of the sixth transistor, and a control terminal coupled to the output terminal;   an eighth transistor having a first current path terminal coupled to the intermediate node, and a control terminal coupled to the first current path terminal of the eighth transistor; and   a ninth transistor having a control terminal coupled to the control terminal of the eighth transistor, a first current path terminal coupled to the output terminal, and a second current path terminal coupled to a second current path terminal of the eighth transistor, wherein the first, second, third, fourth, seventh, eighth, and ninth transistors are of a first type, and wherein the fifth and sixth transistor are of a second type.   
     
     
         16 . The circuit of  claim 15 , wherein the first type is the N-type, and wherein the second type is the P-type. 
     
     
         17 . The circuit of  claim 15 , further comprising:
 first and second voltage rails; and   a current source coupled between the first voltage rail and the input terminal, wherein a second current path terminal of the second transistor is coupled to the first voltage rail, wherein the second current path terminal of the fifth transistor is coupled to the first voltage rail, wherein the second current path terminal of the third transistor is coupled to the second voltage rail, wherein a second current path terminal of the seventh transistor is coupled to the second voltage rail, and wherein the second current path terminal of the eighth transistor is coupled to the second voltage rail.   
     
     
         18 . The circuit of  claim 15 , further comprising an output transistor having a control terminal coupled to the output terminal and a first current path terminal coupled to the second current path terminal of the ninth transistor. 
     
     
         19 . An electronic circuit for generating a first current from a second current, the circuit comprising:
 an output transistor configured to generate the first current;   a first circuit configured to generate a third current representative of the second current and to draw the third current from a first node of the electronic circuit;   a second circuit configured to generate a fourth current representative of the first current flowing through the output transistor and to supply the fourth current to the first node; and   a third circuit coupled to the first node to receive a fifth current representative of a difference between the third and fourth currents, the third circuit being configured to generate a sixth current representative of the fifth current and to draw the sixth current from a control terminal of the output transistor, wherein the first circuit is further configured to supply a seventh current to the control terminal of the output transistor, the seventh current being determined by the second current.   
     
     
         20 . The electronic circuit of  claim 19 , wherein:
 a first transistor of the first circuit comprises a first current path terminal coupled to the control terminal of the output transistor and is disconnected from the first node; and   a second transistor of the first circuit comprises a first current path terminal coupled to a first branch of a current mirror of the first circuit, and a second current path terminal and a control terminal coupled to a second node configured to receive the second current and to a control terminal of the first transistor.