Carrier injection control fast recovery diode structures and methods of fabrication

Abstract

Semiconductor devices and methods of fabrication are provided. The semiconductor device includes a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD) to control charge injection by lowering carrier storage. The device can have a first conductivity type semiconductor substrate, and a drift region that includes a doped buffer region, a doped middle region and a doped field stop region or carrier storage region. The device can also include a second conductivity type shield region including a deep junction encircling (or substantially laterally beneath) the buffer region and a second conductivity type shallow junction anode region in electrical contact with a second conductivity type anode electrode. The deep junction can have a range of doping concentrations surrounding the buffer regions to deplete buffer charge laterally as well as vertically to prevent premature device breakdown. The first conductivity type may be N type and the second conductivity type may be P type.

What is claimed is: 
     
         1 . A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
 forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising a buffer region on the top region of the drift region, a lightly doped middle region, and a medium level doped charge storage region;   forming trenches, in the drift region, having depth ranging from 2-6 microns;   ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially spreading laterally beneath the buffer region of the first conductivity type;   filling the trenches with poly silicon having lightly doped second conductivity type impurities encircling the buffer region of the first conductivity type;   after planarizing the poly silicon in the trenches, ion implanting dopants of the second conductivity type to define a lightly doped anode;   depositing Boron-doped Phospho Silicate Glass layer (BPSG) or Phospho Silicate Glass layer (PSG) for defining a contact;   depositing poly silicon and ion implanting with the second conductivity type dopants with varying doping level for, at least in part, controlling carrier injection.   
     
     
         2 . The method of  claim 1 , further comprising forming a high voltage termination region surrounding an active area, the high voltage termination region comprising a plurality of floating rings of additional poly silicon filled trenches on top of the second conductivity type shield region. 
     
     
         3 . The method of  claim 1 , further comprising forming a Schottky contact on the surface of the buffer region surrounded on two or all sides by the shield region for forming a hybrid schottky and junction Fast Recovery Diode (HSJ FRD). 
     
     
         4 . A method of fabricating a Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
 forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising:
 a medium level doped buffer region on the top region of the drift region, 
 a lightly doped middle region, and 
 a medium level doped field stop region; 
   forming trenches, in the drift region, having depth ranging from 2-6 microns;   ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;   filling trenches with a dielectric layer encircling medium level doped buffer region of the drift region;   forming a shallow and lightly doped junction anode region of the second conductivity type;   depositing a poly silicon layer doped by ion implantation as an anode, of the second conductivity type, after depositing and defining contact regions;   depositing a frontside metal and passivation layer; and   grinding a FRD wafer backside and etching to thin the wafer and depositing backside metal Titanuim:Nickel:Silver (Ti:Ni:Ag) alloy or gold (Au) to form at least an anode electrode;   wherein the first conductivity type is N type and the second conductivity type is P type.   
     
     
         5 . A method of fabrication Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
 forming a drift region of a first conductivity type on top of a lightly doped semiconductor substrate, the drift region supporting blocking of high voltage and comprising:
 a buffer region on the top region of the drift region, 
 a lightly doped middle region, and 
 a medium level doped field stop region; 
   forming trenches, in the drift region, having depth ranging from 2-6 microns;   ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;   filling trenches;   forming a shallow junction anode region of the second conductivity type;   depositing a poly silicon layer doped by ion implantation as an anode, of the second conductivity type, after depositing and defining contact regions;   depositing a frontside metal and passivation layer;   grinding a FRD wafer backside and etching to thin the wafer down to a predetermined thickness;   sputtering N+ silicon or N+ poly S as a cathode to a whole or certain portion of the wafer backside, depositing a dielectric layer to the wafer backside, wherein cathode contacts are opened via a mask before the sputtering of the N+ Silicon or N+ poly Si; and   depositing metal Ti:Ni:Ag or Au to the wafer backside and sintering for completing fabrication of the wafer for the FRD;   wherein the first conductivity type is N type and the second conductivity type is P type.   
     
     
         6 . The method of  claim 5 ,
 wherein the buffer region of the drift region is medium level doped; and   wherein the trenches are filled with the second conductivity type poly silicon encircling the medium level doped buffer region.   
     
     
         7 . The method of  claim 5 ,
 wherein the buffer region of the drift region is high level doped; and   wherein the trenches are filled with a dielectric (SiO 2 ) and a CMP dielectric layer to planarize a surface of the wafer surrounding the buffer region.   
     
     
         8 . A method of fabrication Charge Injection Controlled (CIC) Fast Recovery Diode (FRD), the method comprising:
 forming a drift region of a first conductivity type on top of a heavily doped semiconductor substrate by epitaxial growth, the drift region supporting blocking of high voltage and comprising:
 a medium level doped buffer region on the top region of the drift region, 
 a lightly doped middle region, and 
 a medium level doped field stop region; 
   forming trenches, in the drift region, having depth ranging from 2-6 microns;   ion implanting dopants of a second conductivity type into the trenches for forming a shield region of the second conductivity type, the shield region comprising a deep junction substantially expanding laterally in the lightly doped middle region;   filling trenches with poly silicon of the second conductivity type formed by ion implantation surrounding two or all sides of the medium level doped buffer region;   an anode electrode electrically in contact with the second conductivity type poly silicon filling the trenches;   varying the doping concentration of the poly silicon filling the trenches to control, at least in part, the carrier injection and resulting reverse recovery time of the FRD;   depositing a BPSG or PSG for defining contact regions;   depositing metal and passivation layer; and   grinding a FRD wafer backside and etching to thin the wafer down to a predetermined thickness and depositing backside metal Ti:Ni:Ag alloy or Au.   
     
     
         9 . The method of  claim 8 , further comprising forming side wall spacers, the forming including depositing or thermally growing oxide inside the trenches reactive-ion etching (RIE) etching the oxide from the bottom of the trenches before filling the trenches.