Addition instructions with independent carry chains

Abstract

A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

What is claimed is: 
     
         1 . An apparatus comprising:
 decoder circuitry to decode an instruction, the instruction to identify a location of a first operand and to identify a location of a second operand; and   execution circuitry to execute the decoded instruction to perform an unsigned addition of the first operand, the second operand, and a carry flag to generate a result, and store the result.   
     
     
         2 . The apparatus of  claim 1 , wherein the identified location of the first operand is a register. 
     
     
         3 . The apparatus of  claim 1 , wherein the execution circuitry is to update the carry flag during execution of the decoded instruction. 
     
     
         4 . The apparatus of  claim 3 , wherein the carry flag is a flag of a flags register. 
     
     
         5 . The apparatus of  claim 4 , wherein the execution circuitry is to not modify other arithmetic flags of the flags register during execution of the decoded instruction. 
     
     
         6 . The apparatus of  claim 1 , wherein the result is to be stored in the identified location of the first operand. 
     
     
         7 . A method comprising:
 decoding an instruction, the instruction to identify a location of a first operand and to identify a location of a second operand; and   executing the decoded instruction to perform an unsigned addition of the first operand, the second operand, and a carry flag to generate a result, and store the result.   
     
     
         8 . The method of  claim 7 , wherein the identified location of the first operand is a register. 
     
     
         9 . The method of  claim 7 , wherein the executing updates the carry flag. 
     
     
         10 . The method of  claim 9 , wherein the carry flag is a flag of a flags register. 
     
     
         11 . The method of  claim 10 , wherein the executing does not modify other arithmetic flags of the flags register. 
     
     
         12 . The method of  claim 7 , wherein the result is stored in the identified location of the first operand. 
     
     
         13 . A system comprising:
 a memory to store an instruction; and   a processor coupled to the memory, the processor comprising:
 decoder circuitry to decode the instruction, the instruction to identify a location of a first operand and to identify a location of a second operand, and 
 execution circuitry to execute the decoded instruction to perform an unsigned addition of the first operand, the second operand, and a carry flag to generate a result, and store the result. 
   
     
     
         14 . The system of  claim 13 , wherein the identified location of the first operand is a register. 
     
     
         15 . The system of  claim 13 , wherein the execution circuitry is to update the carry flag during execution of the decoded instruction. 
     
     
         16 . The system of  claim 15 , wherein the carry flag is a flag of a flags register. 
     
     
         17 . The system of  claim 16 , wherein the execution circuitry is to not modify other arithmetic flags of the flags register during execution of the decoded instruction. 
     
     
         18 . The system of  claim 13 , wherein the result is to be stored in the identified location of the first operand.