Technologies for low-latency cryptography for processor-accelerator communication

Abstract

Technologies for secure data transfer include a computing device having a processor, an accelerator, and a security engine, such as a direct memory access (DMA) engine or a memory-mapped I/O (MMIO) engine. The computing device initializes the security engine with an initialization vector and a secret key. During initialization, the security engine pre-fills block cipher pipelines and pre-computes hash subkeys. After initialization, the processor initiates a data transfer, such as a DMA transaction or an MMIO request, between the processor and the accelerator. The security engine performs an authenticated cryptographic operation for the data transfer operation. The authenticated cryptographic operation may be AES-GCM authenticated encryption or authenticated decryption. The security engine may perform encryption or decryption using multiple block cipher pipelines. The security engine may calculate an authentication tag using multiple Galois field multipliers. Other embodiments are described and claimed.

1 . An apparatus comprising:
 one or more processors coupled to or host one or more of a security engine circuitry, an initialization manager circuitry, and a transfer manager circuitry, wherein:   the initialization manager circuitry to initialize the security engine circuitry with an initialization vector and a secret key;   the transfer manager circuitry to initiate a data transfer operation between a trusted execution environment and an accelerator device in response to initialization of the security engine circuitry, wherein initiating the data transfer operation includes initiating a memory-mapped input/output (I/O) operation with an input data block; and   the security engine circuitry to perform an authenticated cryptographic operation associated with the data transfer operation.   
     
     
         2 . The apparatus of  claim 1 , wherein in performing the authenticated cryptographic operation, the security engine circuitry is further to:
 perform a cryptographic operation with a block cipher pipeline on the input data block to generate an output data block; and   generate a final authentication tag value based on a ciphertext block, wherein the ciphertext block comprises the input data block or the output data block.   
     
     
         3 . The apparatus of  claim 1 , wherein:
 the transfer manager circuitry is further to facilitate the trusted execution environment to (i) calculate an expected authentication tag value associated with the data transfer operation, and (ii) write the expected authentication tag value to the security engine circuitry; and   the security engine circuitry is further to compare the expected authentication tag value with the final authentication tag value.   
     
     
         4 . The apparatus of  claim 2 , wherein in performing the authenticated cryptographic operation, the security engine circuitry is further to:
 read the input data block;   bitwise exclusive OR the input data block with an output of the block cipher pipeline to generate the output data block; and   insert a counter block into a block cipher pipeline in response to the bitwise exclusive ORing and in response to comparing the expected authentication tag value with the final authentication tag value.   
     
     
         5 . The apparatus of  claim 4 , wherein the security engine circuitry comprises one or more block cipher pipelines and one or more field multipliers, wherein the one or more block cipher pipelines include one or more Advanced Encryption Standard (AES) pipelines, and wherein the one or more field multipliers include one or more Galois field multipliers. 
     
     
         6 . The apparatus of  claim 1 , wherein the security engine circuitry to initialize an initial counter block as a function of the initialization vector, wherein the initial counter block is utilized in insertion of counter blocks in the one or more block cipher pipelines. 
     
     
         7 . The apparatus of  claim 1 , wherein the one or more processors are coupled to a memory and comprise one or more applications processors or one or more graphics processors. 
     
     
         8 . A method comprising:
 initializing, by an initialization manager circuitry, a security engine circuitry with an initialization vector and a secret key, wherein the security engine circuitry is coupled to one or more processors further coupled to the initialization manager circuitry and a transfer manager circuitry;   initiating, by the transfer manager circuitry, a data transfer operation between a trusted execution environment and an accelerator device in response to initialization of the security engine circuitry, wherein initiating the data transfer operation includes initiating a memory-mapped input/output (I/O) operation with an input data block; and   performing, by the security engine circuitry, an authenticated cryptographic operation associated with the data transfer operation.   
     
     
         9 . The method of  claim 8 , wherein performing the authenticated cryptographic operation comprises:
 performing, by the security engine circuitry, a cryptographic operation with a block cipher pipeline on the input data block to generate an output data block; and   generating, by the security engine circuitry, a final authentication tag value based on a ciphertext block, wherein the ciphertext block comprises the input data block or the output data block.   
     
     
         10 . The method of  claim 8 , further comprising:
 facilitating, by the transfer manager circuitry, the trusted execution environment to (i) calculate an expected authentication tag value associated with the data transfer operation, and (ii) write the expected authentication tag value to the security engine circuitry; and   comparing, by the security engine circuitry, the expected authentication tag value with the final authentication tag value.   
     
     
         11 . The method of  claim 9 , wherein performing the authenticated cryptographic operation comprises:
 reading, by the security engine circuitry, the input data block;   bitwise exclusive ORing, by the security engine circuitry, the input data block with an output of the block cipher pipeline to generate the output data block; and   inserting, by the security engine circuitry, a counter block into a block cipher pipeline in response to the bitwise exclusive ORing and in response to comparing the expected authentication tag value with the final authentication tag value.   
     
     
         12 . The method of  claim 11 , wherein the security engine circuitry comprises one or more block cipher pipelines and one or more field multipliers, wherein the one or more block cipher pipelines include one or more Advanced Encryption Standard (AES) pipelines, and wherein the one or more field multipliers include one or more Galois field multipliers. 
     
     
         13 . The method of  claim 8 , further comprising initializing, by the security engine circuitry, an initial counter block as a function of the initialization vector, wherein the initial counter block is utilized in insertion of counter blocks in the one or more block cipher pipelines, wherein the one or more processors are coupled to a memory and comprise one or more applications processors or one or more graphics processors. 
     
     
         14 . A computer-readable medium having stored thereon instructions which, when executed, cause one or more processors to facilitate operations comprising:
 initializing, by an initialization manager circuitry, a security engine circuitry with an initialization vector and a secret key, wherein the security engine circuitry is coupled to the one or more processors further coupled to the initialization manager circuitry and a transfer manager circuitry;   initiating, by the transfer manager circuitry, a data transfer operation between a trusted execution environment and an accelerator device in response to initialization of the security engine circuitry, wherein initiating the data transfer operation includes initiating a memory-mapped input/output (I/O) operation with an input data block; and   performing, by the security engine circuitry, an authenticated cryptographic operation associated with the data transfer operation.   
     
     
         15 . The computer-readable medium of  claim 14 , wherein the operations further comprise:
 performing, by the security engine circuitry, a cryptographic operation with a block cipher pipeline on the input data block to generate an output data block; and   generating, by the security engine circuitry, a final authentication tag value based on a ciphertext block, wherein the ciphertext block comprises the input data block or the output data block.   
     
     
         16 . The computer-readable medium of  claim 14 , wherein the operations further comprise:
 facilitating, by the transfer manager circuitry, the trusted execution environment to (i) calculate an expected authentication tag value associated with the data transfer operation, and (ii) write the expected authentication tag value to the security engine circuitry; and   comparing, by the security engine circuitry, the expected authentication tag value with the final authentication tag value.   
     
     
         17 . The computer-readable medium of  claim 15 , wherein the operations further comprise:
 reading, by the security engine circuitry, the input data block;   bitwise exclusive ORing, by the security engine circuitry, the input data block with an output of the block cipher pipeline to generate the output data block; and   inserting, by the security engine circuitry, a counter block into a block cipher pipeline in response to the bitwise exclusive ORing and in response to comparing the expected authentication tag value with the final authentication tag value.   
     
     
         18 . The computer-readable medium of  claim 17 , wherein the security engine circuitry comprises one or more block cipher pipelines and one or more field multipliers, wherein the one or more block cipher pipelines include one or more Advanced Encryption Standard (AES) pipelines, and wherein the one or more field multipliers include one or more Galois field multipliers. 
     
     
         19 . The computer-readable medium of  claim 14 , wherein the operations further comprise initializing, by the security engine circuitry, an initial counter block as a function of the initialization vector, wherein the initial counter block is utilized in insertion of counter blocks in the one or more block cipher pipelines. 
     
     
         20 . The computer-readable medium of  claim 14 , wherein the one or more processors are coupled to a memory and comprise one or more applications processors or one or more graphics processors.