Processor with multiple execution pipelines

Abstract

An apparatus and method system and method for increasing performance in a processor or other instruction execution device while minimizing energy consumption. A processor includes a first execution pipeline and a second execution pipeline. The first execution pipeline includes a first decode unit and a first execution control unit coupled to the first decode unit. The first execution control unit is configured to control execution of all instructions executable by the processor. The second execution pipeline includes a second decode unit, and a second execution control unit coupled to the second decode unit. The second execution control unit is configured to control execution of a subset of the instructions executable via the first execution control unit.

What is claimed is: 
     
         1 . A processing device comprising:
 an instruction fetch unit;   a first decode unit coupled to the instruction fetch unit;   a first execution control unit coupled to the first decode unit;   a second decode unit coupled to the instruction fetch unit;   a second execution control unit coupled to the second decode unit; and   a set of execution units coupled to the first execution control unit and the second execution control unit wherein:
 the first decode unit and the first execution control unit are configured to cause the set of execution units to execute any instruction of a first instruction set; and 
 the second decode unit and the second execution control unit are configured to cause the set of execution units to execute any instruction of a second instruction set that is a subset of the first instruction set such that a remainder of the first instruction set is not in the second instruction set. 
   
     
     
         2 . The processing device of  claim 1  further comprising a register file coupled to the set of execution units, wherein each instruction in the second instruction set utilizes a register operand mode, an immediate addressing mode, or a combination thereof. 
     
     
         3 . The processing device of  claim 1 , wherein the second instruction set includes only reduced instruction set computer (RISC) instructions and the remainder of the first instruction set includes complex instruction set computer (CISC) instructions. 
     
     
         4 . The processing device of  claim 1 , wherein the second instruction set includes only instructions that can be executed in one clock cycle and the remainder of the first instruction set includes instructions that are executed in more than one clock cycle. 
     
     
         5 . The processing device of  claim 1 , wherein:
 the set of execution units includes an arithmetic logic unit and a remainder of the set of execution units;   the first execution control unit and the second execution control unit are each configured to control the arithmetic logic unit;   the first execution control unit is configured to control the remainder of the set of execution units; and   the second execution control unit is not configured to control the remainder of the set of execution units.   
     
     
         6 . The processing device of  claim 5 , wherein the remainder of the set of execution units includes at least one of: a shift unit, a multiply unit, a floating point unit, or a load/store unit. 
     
     
         7 . The processing device of  claim 1 , wherein:
 the first execution control unit is configured to cause the set of execution units to execute an instruction of the first instruction set in a first number of pipeline stages; and   the second execution control unit is configured to cause the set of execution units to execute an instruction of the second instruction set in a second number of pipeline stages that is less than the first number of pipeline stages.   
     
     
         8 . The processing device of  claim 1 , wherein:
 the instruction fetch unit is configured to receive a first instruction and provide the first instruction to either the first execution control unit or the second execution control unit based on whether the first instruction is in the second instruction set.   
     
     
         9 . The processing device of  claim 1 , wherein the first decode unit and the second decode unit are coupled to operate in parallel. 
     
     
         10 . The processing device of  claim 8 , wherein the first execution control unit is configured to cause the set of execution units to execute a first instruction and the second execution control unit is configured to cause the set of execution units to execute a second instruction in parallel with the first instruction. 
     
     
         11 . A processing device comprising:
 a first decode unit;   a second decode unit coupled in parallel with the first decode unit;   a first execution control unit coupled to the first decode unit;   a second execution control unit coupled to the second decode unit; and   a set of execution units coupled to the first execution control unit and the second execution control unit wherein:
 the first decode unit and the first execution control unit are configured to cause the set of execution units to execute a first instruction having a first addressing mode and a second instruction having a second addressing mode that is different from the first addressing mode; and 
 the second decode unit and the second execution control unit are configured to cause the set of execution units to execute the first instruction having the first addressing mode and not configured to cause the set of execution units to execute the second instruction having the second addressing mode. 
   
     
     
         12 . The processing device of  claim 11 , wherein the first addressing mode includes at least one of a register operand mode or an immediate addressing mode. 
     
     
         13 . The processing device of  claim 11 , wherein the first instruction utilizes only a register operand mode, an immediate addressing mode, or a combination thereof. 
     
     
         14 . The processing device of  claim 11 , wherein the second addressing mode is not a register operand mode or an immediate addressing mode. 
     
     
         15 . The processing device of  claim 11 , wherein:
 the first execution control unit includes a first number of execution stage circuits; and   the second execution control unit includes a second number of execution stage circuits that is less than the first number of execution stage circuits.   
     
     
         16 . The processing device of  claim 15 , wherein:
 the second decode unit and the second execution control unit are configured to cause the set of execution units to execute the first instruction in a single clock cycle; and   the first decode unit and the first execution control unit are configured to cause the set of execution units to execute the second instruction in more than one clock cycle.   
     
     
         17 . The processing device of  claim 13 , wherein:
 the set of execution units includes an arithmetic logic unit and a remainder of the set of execution units;   the first execution control unit and the second execution control unit are each configured to control the arithmetic logic unit; and   the first execution control unit but not the second execution control unit is configured to control the remainder of the set of execution units.   
     
     
         18 . The processing device of  claim 17 , wherein the remainder of the set of execution units includes at least one of: a shift unit, a multiply unit, a floating point unit, or a load/store unit. 
     
     
         19 . The processing device of  claim 11  further comprising an instruction fetch unit, wherein the first decode unit and the second decode unit are coupled to the instruction fetch unit in parallel. 
     
     
         20 . The processing device of  claim 19 , wherein the first execution control unit and the second execution control unit are configured to cause the set of execution units to execute instructions in parallel.