Data communications with enhanced speed mode

Abstract

An interconnect controller for a data processing platform includes a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer, and a physical layer controller coupled to the data link layer controller and adapted to be coupled to a communication link. The physical layer controller operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount. In response to performing a link initialization, the interconnect controller performs at least one setup operation to select a speed, and subsequently operates the communication link using a selected speed.

What is claimed is: 
     
         1 . An interconnect controller for a data processing platform comprising:
 a data link layer controller for selectively receiving data packets from and sending data packets to a higher protocol layer; and   a physical layer controller coupled to said data link layer controller and adapted to be coupled to a communication link, said physical layer controller operating according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount,   wherein in response to performing a link initialization, the interconnect controller:
 performs at least one setup operation to select a selected speed; and 
 subsequently operates the communication link using said selected speed. 
   
     
     
         2 . The interconnect controller of  claim 1 , wherein:
 each of said plurality of enhanced speeds is between a first predetermined link speed and a second predetermined link speed specified by a published standard.   
     
     
         3 . The interconnect controller of  claim 1 , wherein:
 each of said plurality of enhanced speeds is higher than a highest published speed supported by a published standard.   
     
     
         4 . The interconnect controller of  claim 1 , wherein:
 the interconnect controller subsequently operates the communication link by programming a loop divider of a phase locked loop.   
     
     
         5 . The interconnect controller of  claim 4 , wherein:
 the interconnect controller determines said selected speed by accessing at least one enhanced speed mode capability register.   
     
     
         6 . The interconnect controller of  claim 1 , wherein:
 said physical layer controller is compliant with the Peripheral Component Interconnect Express (PCIe) Base Specification;   the interconnect controller queries the data processing platform to determine whether an enhanced speed mode is permitted; and   the interconnect controller is part of a PCIe root complex that determines an enhanced speed for the interconnect controller based on capabilities of an upstream port of an endpoint as a highest mutually supported speed by the interconnect controller and said upstream port of said endpoint.   
     
     
         7 . The interconnect controller of  claim 1 , wherein:
 said higher protocol layer comprises one of a PCIe transaction layer and a cache coherent interconnect for accelerators (CCIX) transaction layer.   
     
     
         8 . The interconnect controller of  claim 1 , wherein:
 said physical layer controller further operating according to said predetermined protocol selectively at one of a first predetermined link speed specified by a published standard and said plurality of enhanced speeds.   
     
     
         9 . A data processing platform comprising:
 a basic input/output system (BIOS);   a data processor comprising:
 a central processing unit coupled to and responsive to said BIOS to execute an initialization procedure; and 
 an interconnect controller coupled to said central processing unit and adapted to be coupled to a communication link that operates according to a predetermined protocol selectively at one of a plurality of enhanced speeds that are not specified by any published standard and are separated from each other by the same predetermined amount; 
   wherein said BIOS comprises instructions that when executed by said central processing unit cause said interconnect controller to:
 perform at least one setup operation to select a speed; and 
 subsequently operate the communication link using a selected speed. 
   
     
     
         10 . The data processing platform of  claim 9 , wherein:
 each of said plurality of enhanced speeds is between a first predetermined link speed and a second predetermined speed specified by a published standard.   
     
     
         11 . The data processing platform of  claim 9 , wherein:
 each of said plurality of enhanced speeds is higher than a highest published speed supported by a published standard.   
     
     
         12 . The data processing platform of  claim 9 , wherein:
 the interconnect controller subsequently operates the communication link by programming a loop divider of a phase locked loop.   
     
     
         13 . The data processing platform of  claim 12 , wherein:
 the interconnect controller determines said selected speed by accessing at least one enhanced speed mode capability register.   
     
     
         14 . The data processing platform of  claim 9 , wherein:
 the interconnect controller is compliant with the Peripheral Component Interconnect Express (PCIe) Base Specification; and   the interconnect controller queries the data processing platform to determine whether an enhanced speed mode is permitted.   
     
     
         15 . The data processing platform of  claim 9 , wherein:
 the interconnect controller is part of a PCIe root complex that determines an enhanced speed for the interconnect controller based on capabilities of an upstream port of an endpoint as a highest mutually supported speed by the interconnect controller and said upstream port of said endpoint.   
     
     
         16 . A method for use in a data processing platform having an interconnect controller that operates a communication link according to a published standard, comprising:
 querying the data processing platform to determine whether an enhanced speed mode is permitted;   performing at least one setup operation to select an operating speed for operating according to a predetermined protocol from among a plurality of enhanced speeds that are not specified by the published standard and are separated from each other by the same predetermined amount; and   subsequently operating the communication link using said operating speed.   
     
     
         17 . The method of  claim 16 , wherein:
 the published standard supports a first predetermined link speed and a second predetermined link speed greater than said first predetermined link speed; and   said operating speed is between said first predetermined link speed and said second predetermined link speed.   
     
     
         18 . The method of  claim 16 , wherein:
 said plurality of enhanced speeds are greater than a first predetermined link speed, wherein said first predetermined link speed is a highest published speed supported by said published standard.   
     
     
         19 . The method of  claim 18 , wherein:
 subsequently operating the communication link using said operating speed comprises programming a loop divider of a phase locked loop.   
     
     
         20 . The method of  claim 19 , further comprising:
 determining said operating speed by accessing at least one enhanced speed mode capability register.