Electrical circuit for pre-regulation power management

Abstract

A system may include a switch, a multiple stage voltage converter, and a regulation circuit. The switch may generate a pre-regulation signal based on an input signal. The multiple stage voltage converter may generate an output signal based on the input signal using a clock. The regulation circuit may generate a regulation signal based on the output signal and may generate a clock reference based on at least one of the pre-regulation signal and the regulation signal. The regulation circuit may generate the clock based on at least one of the pre-regulation signal, the regulation signal, and the clock reference and determine whether a voltage level of the regulation signal is within a range. If the voltage level of the regulation signal is within the range, the regulation circuit may generate a switch signal. The switch may adjust a voltage level of the pre-regulation signal based on the switch signal.

What is claimed is: 
     
         1 . A system comprising:
 a multiple stage voltage converter configured to generate an output signal based on an input signal and a clock signal; and   a regulation circuit configured to:
 generate the clock signal based on a voltage level of a pre-regulation input signal; 
 generate a regulation signal based on the output signal; and 
 determine whether a voltage level of the regulation signal is within a voltage range, and
 responsive to the voltage level of the regulation signal being within the voltage range, the regulation circuit is further configured to generate a switch control signal to cause the voltage level of the pre-regulation input signal to be adjusted. 
 
   
     
     
         2 . The system of  claim 1  further comprising a switching circuit configured to:
 generate the pre-regulation input signal based on the input signal and the regulation signal; and 
 adjust the voltage level of the pre-regulation input signal based on the switch control signal. 
 
     
     
         3 . The system of  claim 2 , wherein the switch control signal causes the switching circuit to transition from a closed position to an open position to cause the voltage level of the pre-regulation input signal to approach zero volts. 
     
     
         4 . The system of  claim 3 , the switching circuit comprises a first switching circuit configured to generate the pre-regulation input signal based on the input signal. 
     
     
         5 . The system of  claim 4 , the switching circuit further comprises a second switching circuit configured to generate a second switch control signal based on the switch control signal, wherein the first switching circuit is configured to transition from a closed position to an open position based on the second switch control signal to cause the voltage level of the pre-regulation input signal to approach zero volts. 
     
     
         6 . The system of  claim 4  further comprising:
 a resistive circuit; and 
 a switch diode electrically coupled to the first switching circuit, the resistive circuit, and ground, wherein the switch diode is configured to operate as a Zener clamp and the resistive circuit is configured to provide a bias voltage to the diode. 
 
     
     
         7 . The system of  claim 1 , wherein a voltage level and a frequency of the clock signal is based on the voltage level of the pre-regulation input signal. 
     
     
         8 . The system of  claim 1 , wherein the clock signal is further based on a voltage level of the regulation signal. 
     
     
         9 . The system of  claim 1 , the regulation circuit comprising a bandgap reference (BGR) circuit configured to generate a clock reference signal based on the voltage level of the pre-regulation input signal, wherein the clock signal is generated based on the clock reference signal. 
     
     
         10 . The system of  claim 9 , wherein the BGR circuit is further configured to generate an under-voltage lockout (UVLO) reference signal based on the pre-regulation input signal, the regulation circuit further comprising a UVLO circuit configured to:
 determine whether the voltage level of the regulation signal is within the voltage range; and
 responsive to the voltage level of the regulation signal being within the voltage range, the UVLO circuit is further configured to generate the switch control signal. 
   
     
     
         11 . The system of  claim 10 , wherein the BGR circuit is further configured to generate a low dropout regulator (LDO) reference signal based on the pre-regulation input signal, the regulation circuit further comprising an LDO circuit configured to generate the regulation signal based on the output signal and the LDO reference signal. 
     
     
         12 . The system of  claim 9  further comprising a regulation diode comprising:
 an anode end electrically coupled to the LDO circuit; and 
 a cathode end electrically coupled to the BGR circuit and the switching circuit, wherein the regulation diode is configured to:
 prevent the pre-regulation input signal from reaching the LDO circuit; and 
 provide the regulation signal to the BGR circuit. 
 
 
     
     
         13 . A method, comprising:
 generating an output signal based on an input signal and a clock signal;   generating a regulation signal based on the output signal;   generating the clock signal based on a voltage level of a pre-regulation input signal; and   determining whether a voltage level of the regulation signal is within a voltage range; and
 responsive to the voltage level of the regulation signal being within the voltage range, causing a voltage level of the pre-regulation input signal to be adjusted. 
   
     
     
         14 . The method of  claim 13  further comprising generating the pre-regulation input signal based on the input signal, wherein causing the voltage level of the pre-regulation input signal to be adjusted comprises generating a switch control signal and the voltage level of the pre-regulation input signal is adjusted based on the switch control signal. 
     
     
         15 . The method of  claim 13  further comprising generating a clock reference signal based on a voltage level of the pre-regulation input signal, wherein the clock signal is further based on the clock reference signal. 
     
     
         16 . The method of  claim 13  further comprising generating a first intermediate signal, a second intermediate signal, and a third intermediate signal, wherein the output signal comprises at least one of the first intermediate signal, the second intermediate signal, and the third intermediate signal, wherein the first intermediate signal, the second intermediate signal, and the third intermediate signal are based on the input signal using the clock signal. 
     
     
         17 . A system configured to operate in a pre-regulation state and a regulated state, the system comprising:
 a switching circuit configured to:
 in the pre-regulation state, generate a pre-regulation signal at a voltage level based on an input signal; and 
 in the regulated state, generate the pre-regulation signal at a voltage level that is equal to zero volts; 
   a multiple stage voltage converter configured to:
 in the pre-regulation state, generate the output signal at a voltage level that is equal to zero volts based on the input signal and using a clock signal; and 
 in the regulated state, generate the output signal at a voltage level that is greater than zero volts based on the input signal and using the clock signal; and 
   a regulation circuit configured to:
 in the pre-regulation state:
 generate a regulation signal at a voltage level that is equal to zero volts based on the voltage level of the output signal; and 
 generate the clock signal based on the voltage level of the pre-regulation signal; and 
 
 in the regulated state:
 generate the regulation signal at a voltage level that is greater than zero volts based on the voltage level of the output signal; and 
 generate the clock signal based on the voltage level of the regulation signal. 
 
   
     
     
         18 . The system of  claim 17 , wherein the regulation circuit comprises:
 an oscillator configured to:
 in the pre-regulation state, generate the clock signal based on the voltage level of the pre-regulation input signal and a clock reference signal; and 
 in the regulated stated, generate the clock signal based on the voltage level of the regulation signal and the clock reference signal; and 
   a bandgap reference (BGR) circuit configured to:
 in the pre-regulation state, generate the clock reference signal based on the voltage level of the pre-regulation input signal; and 
 in the regulated state, generate the clock reference signal based on the voltage level of the regulation signal. 
   
     
     
         19 . The system of  claim 18 , wherein in the pre-regulation state, the BGR circuit is further configured to generate an under-voltage lockout (UVLO) reference signal and an low dropout regulator (LDO) reference signal based on the voltage level of the regulation signal, the regulation circuit further comprises:
 an LDO circuit configured to, in the pre-regulation state and the regulated state, generate the regulation signal based on the voltage level of the output signal and the LDO reference signal;   an UVLO circuit configured to:
 in the pre-regulation state, determine whether the voltage level of the regulation signal is within a voltage range; and
 responsive to the voltage level of the regulation signal being within the voltage range, generate a switch control signal to cause the system to transition to the regulated state. 
 
   
     
     
         20 . The system of  claim 17 , wherein the system is further configured to operate in a transition state, wherein in the transition state:
 the switching circuit is configured to transition from a closed position to an open position;   the multiple stage voltage converter is configured to generate the output signal at the voltage level that is greater than zero volts based on the input signal and using the clock signal; and   the regulation circuit is configured to:
 generate the regulation signal at a voltage level that is greater than zero volts based on a voltage level of the output signal; and 
 generate the clock signal based on the voltage level of the pre-regulation signal and the voltage level of the regulation signal.