Time division duplexing receiver with constant impedance for a broadband line terminal with asynchronous transmission

Abstract

A line driver circuit having an amplifier circuit having a differential output, the differential output including a first output terminal and a second output terminal and an impedance switching circuit coupled between the first output terminal and the second output terminal of the amplifier circuit, wherein the impedance switching circuit is configured to reduce or maintain impedance across the first output terminal and the second output terminal of the amplifier circuit.

1 . A line driver circuit, comprising:
 an amplifier circuit having a differential output, the differential output comprising a first output terminal and a second output terminal; and   an impedance switching circuit coupled between the first output terminal and the second output terminal of the amplifier circuit, wherein the impedance switching circuit is configured to reduce or maintain impedance across the first output terminal and the second output terminal of the amplifier circuit.   
     
     
         2 . The line driver circuit of  claim 1 , the amplifier circuit having a differential input, the differential input comprising a first input terminal and a second input terminal. 
     
     
         3 . The line driver circuit of  claim 1 , wherein the impedance switching circuit is configured to reduce or maintain impedance across the first output terminal and the second output terminal of the amplifier circuit when the line driver circuit switches between a first mode and a second mode. 
     
     
         4 . The line driver circuit of  claim 3 , wherein in the first mode, a first switching configuration is established resulting in a first output impedance at the first output terminal and the second output terminal of the amplifier circuit. 
     
     
         5 . The line driver circuit of  claim 4 , wherein in the second mode, a second switching configuration is established resulting in a second output impedance at the first output terminal and the second output terminal of the amplifier circuit, 
     
     
         6 . The line driver circuit of  claim 5 , wherein the second output impedance is less than about 50% of a termination impedance as defined by the first and second termination impedances. 
     
     
         7 . The line driver circuit of  claim 6 , wherein the second output impedance is less than about 20% of the termination impedance. 
     
     
         8 . The line driver circuit of  claim 3 , wherein the first mode includes a transmit mode and the second mode includes a receive mode. 
     
     
         9 . The line driver circuit of  claim 1 , wherein the impedance switching circuit is configured to maintain impedance across the first output terminal and the second output terminal of the amplifier circuit so that a crosstalk on a data line is substantially maintained. 
     
     
         10 . The line driver circuit of  claim 1 , wherein the impedance switching circuit comprises:
 a first impedance;   a first switch coupled in series with the first impedance;   a second switch connected in series with the first switch at a connection node; and   a second impedance connected in series with the second switch,   wherein in a first switching configuration the first and second switches are open, resulting in the impedance switching circuit operating as an open circuit at the first output terminal and the second output terminal of the amplifier circuit.   
     
     
         11 . The line driver circuit of  claim 10 , wherein in the second switching configuration the first and second switches are closed, thereby effectively connecting the first and second impedance together in series between the first output terminal and the second output terminal of the amplifier circuit. 
     
     
         12 . The line driver circuit of  claim 10 , further comprising one of a common mode voltage or a circuit ground coupled to the connection node between the first and second closed switches, thereby balancing a voltage drop across the first and second impedances. 
     
     
         13 . The line driver circuit of  claim 10 , wherein the first and second switches comprise first and second transistors, respectively, and wherein a control terminal of the first and second transistors are connected together to effectuate a turning on or a turning off of the first and second transistors together. 
     
     
         14 . The line driver circuit of  claim 1 , wherein the amplifier is switchable between an active mode and a power down mode, wherein the impedance switching circuit is configured to be set in a first mode when the amplifier is in the active mode and to be set in a second mode when the amplifier is in the power down mode. 
     
     
         15 . The line driver circuit of  claim 14 , wherein the impedance switching circuit is configured to at least partially compensate a change of output impedance of the line driver circuit when the amplifier switches between an active mode and an inactive mode. 
     
     
         16 . The line driver circuit of  claim 1  configured to operate in a time division duplexing (TDD) mode. 
     
     
         17 . A method to operate a line driver circuit, the method comprising:
 operating an impedance switching circuit at an output of an amplifier in a first mode during a first operation, wherein the amplifier is activated, wherein the impedance switching circuit establishes a first impedance configuration during the first operation; and   operating the impedance switching circuit at the output of the amplifier in a second mode during a second operation, wherein the amplifier is deactivated, wherein the impedance switching circuit establishes a second impedance configuration during the second operation;   wherein the impedance switching circuit is configured to reduce or maintain impedance at an output of the amplifier.   
     
     
         18 . The method of  claim 17 , wherein a magnitude of a difference between a first output impedance of the line driver circuit based on the first impedance configuration and a second output impedance of the line driver circuit based on the second impedance configuration is less than a predetermined threshold so as to substantially maintain a crosstalk performance characteristic associated therewith when the line driver circuit switches between the first mode and the second mode. 
     
     
         19 . The method of  claim 17 , wherein the impedance switching circuit is configured to reduce or maintain impedance at an output of the amplifier when the line driver circuit switches between a first mode and a second mode. 
     
     
         20 . The method of  claim 17 , wherein the impedance is maintained across a first output terminal and a second output terminal of the amplifier so that a crosstalk on a data line is substantially maintained.