Image processor and methods for processing an image

Abstract

There may be provided a non-uniform Benes network, that may include a first Benes network portion that has a first number (k) of first inputs and k first outputs; a second Benes network portion that has a second number (j) of second inputs and j second outputs; wherein j is smaller than k; and a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network layer.

1 . An integrated circuit for a non-uniform Benes network, the integrated circuit comprising:
 a first Benes network portion within a non-uniform Benes network, the first Benes network portion including a first number (k) of first inputs and k first outputs;   a second Benes network portion within the non-uniform Benes network, the second Benes network portion including a second number (j) of second inputs and j second outputs, wherein j is smaller than k; and   a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network portion;   wherein:
 the non-uniform Benes network is configured to couple processing units of a two-dimensional array of the integrated circuit; and 
 the integrated circuit includes a two-dimensional integrated circuit. 
   
     
     
         2 . The integrated circuit according to  claim 1 , wherein:
 the k first outputs and the j second outputs form a third number of outputs of the non-uniform Benes network;   the third number of outputs equals a sum of k and j; and   the third number of outputs differs from a power of two.   
     
     
         3 . The integrated circuit according to  claim 1 , wherein k is a power of two. 
     
     
         4 . The integrated circuit according to  claim 1 , wherein the first Benes network portion includes the non-uniform Benes network and wherein the second Benes network portion comprises a portion of the non-uniform Benes network. 
     
     
         5 . The integrated circuit according to  claim 1 , wherein the intermediate layer is immediately followed by a middle layer of the first Benes network portion. 
     
     
         6 . The integrated circuit according to  claim 1 , comprising a configuration unit that is configured to configure each of: the first Benes network portion, the second Benes network portion, and the set of multiplexers. 
     
     
         7 . The integrated circuit according to  claim 6 , wherein the configuration unit comprises configuration registers, input registers, a write circuit, and a network that couples the input registers to the write circuit. 
     
     
         8 . The integrated circuit according to  claim 7 , wherein a subset of inputs of the non-uniform Benes network are directly coupled to outputs of the non-uniform Benes network. 
     
     
         9 . The integrated circuit according to  claim 7 , wherein one or more inputs of the non-uniform Benes network are coupled to one or more XOR logic gates. 
     
     
         10 . The integrated circuit according to  claim 7 , wherein the configuration registers comprise a first group of configuration registers for configuring the first Benes network portion, a second group of configuration registers for configuring the second Benes network portion, and one or more configuration registers for configuring the set of multiplexers. 
     
     
         11 . The integrated circuit according to  claim 7 , wherein the write circuit comprises a masking unit for configuring groups of switches based on masking bits. 
     
     
         12 . The integrated circuit according to  claim 7 , wherein the non-uniform Benes network is configured to provide address information to the write circuit, the address information identifying inputs of switches of the non-uniform Benes network to be configured by configuration information stored in the input registers. 
     
     
         13 . The integrated circuit according to  claim 12 , wherein the configuration unit is configured to calculate addresses of input of switches of a path formed within the non-uniform Benes network by applying an iterative process, starting from an address of an input switch of the path to an address of an output switch of the path. 
     
     
         14 . The integrated circuit according to  claim 12 , wherein the non-uniform Benes network is configured to calculate an address of a switch input within a path formed within the non-uniform Benes network based on an address of an output switch of the path and one or more configuration bits. 
     
     
         15 . The integrated circuit according to  claim 1 , wherein the set of switches of the intermediate layer of the first Benes network portion is a part of a total number of switches of the intermediate layer of the first Benes network portion. 
     
     
         16 . The integrated circuit according to  claim 1 , wherein j is smaller than half of k, and wherein the set of switches of the intermediate layer of the first Benes network portion include 2*j switches. 
     
     
         17 . The integrated circuit according to  claim 1 , wherein the set of switches of the intermediate layer of the first Benes network portion are arranged as spaced apart subsets of switches. 
     
     
         18 . The integrated circuit according to  claim 1 , wherein the first Benes network portion includes a first Benes network, the second Benes network portion comprises a subset of layers of a second Benes network, and wherein some layers of the first Benes network portion are configured to operate as a first portion of the second Benes network portion. 
     
     
         19 . The integrated circuit according to  claim 1 , wherein the two-dimensional array of the processing units comprises at least six rows, and wherein a number of columns of the two-dimensional array exceeds a number of rows of the two-dimensional array. 
     
     
         20 . The integrated circuit according to  claim 1 , wherein the two-dimensional array of the processing units is configured to perform image processing operations. 
     
     
         21 . The integrated circuit according to  claim 1 , wherein:
 each processing unit of at least two of the processing units of the two-dimensional array of the processing units is directly coupled to some processing units of the two-dimensional array of the processing units;   each processing unit is indirectly coupled to some other processing units of the two-dimensional array of the processing units; and   each processing unit includes a relay channel for relaying data between different relay ports of each processing unit.   
     
     
         22 . The integrated circuit according to  claim 21 , wherein the relay channel exhibits zero latency. 
     
     
         23 . A method for operating a non-uniform Benes network, the method comprising:
 conveying data through the non-uniform Benes network, the non-uniform Benes network included in an integrated circuit and configured to couple processing units of a two-dimensional array of the integrated circuit, wherein the non-uniform Benes network comprises:
 a first Benes network portion that has a first number (k) of first inputs and k first outputs; 
 a second Benes network portion that has a second number (j) of second inputs and j second outputs, wherein j is smaller than k; and 
 a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network portion; 
   wherein the integrated circuit includes a two-dimensional integrated circuit.   
     
     
         24 . A non-transitory computer readable medium that stores instructions for operating a non-uniform Benes network that is included in an integrated circuit and is configured to couple processing units of a two-dimensional array of processing units of the integrated circuit, which when executed by a computer, cause the computer to perform operations comprising:
 conveying data through the non-uniform Benes network, wherein the non-uniform Benes network comprises:
 a first Benes network portion that has a first number (k) of first inputs and k first outputs; 
 a second Benes network portion that has a second number (j) of second inputs and j second outputs, wherein j is smaller than k; and 
 a set of multiplexers that are coupled between a set of switches of an intermediate layer of the first Benes network portion and a first layer of the second Benes network portion; 
   wherein the integrated circuit includes a two-dimensional integrated circuit.