Variable low resistance line nonvolatile memory device and method for operating same

Abstract

A variable low-resistance line memory device and an operating method thereof are provided. The memory device includes: a base including a spontaneous polarizable material; a gate arranged adjacent to the base; at least two polarization regions formed in the base by applying an electric field to the base through the gate, the at least two polarization regions having polarization in different directions from each other; a variable low-resistance line corresponding to a boundary between the at least two polarization regions selectively having polarization in different directions from each other; a source located to contact the variable low-resistance line; and a drain located to contact the variable low-resistance line, wherein the variable low-resistance line is formed in a region of the base, the region having a lower electrical resistance than other regions of the base adjacent to the variable low-resistance line.

What is claimed is: 
     
         1 . A non-volatile memory device comprising:
 a base comprising a spontaneous polarizable material;   a gate arranged adjacent to a surface of the base;   at least two polarization regions formed in the base by applying an electric field to the base through the gate, the at least two polarization regions having polarization in different directions from each other;   a variable low-resistance line corresponding to a boundary between the at least two polarization regions selectively having polarization in different directions from each other;   a source located to contact the variable low-resistance line; and   a drain located to contact the variable low-resistance line,   wherein the variable low-resistance line is formed in a region of the base, the region having a lower electrical resistance than other regions of the base adjacent to the variable low-resistance line,   the variable low-resistance line electrically connects the source to the drain,   the variable low-resistance line is located around e the gate in a surface direction of the base.   
     
     
         2 . The non-volatile memory device of  claim 1 , wherein the at least two polarization regions comprise a first region having a polarization in a first direction and a second region selectively having a polarization in a second direction opposite to the first direction, and
 the variable low-resistance line is between the first region and the second region.   
     
     
         3 . The non-volatile memory device of  claim 2 , wherein the first region and the second region have a same thickness. 
     
     
         4 . The non-volatile memory device of  claim 2 , wherein the second region has a first thickness, and the first region includes a portion having a second thickness greater than the first thickness. 
     
     
         5 . The non-volatile memory device of  claim 2 , wherein the gate is provided to apply an electric field to one of the first region and the second region. 
     
     
         6 . The non-volatile memory device of  claim 5 , wherein the gate is provided to control a polarization direction of a region that is adjacent to at least the gate from among the first region and the second region. 
     
     
         7 . The non-volatile memory device of  claim 1 , wherein the variable low-resistance line is generated or disappeared according to the control of the at least two polarization regions by controlling an electric field through the gate, and after the electric field is removed, a shape of the variable low-resistance line is maintained constant to have non-volatile characteristics of information. 
     
     
         8 . The non-volatile memory device of  claim 1 , wherein a depth of the variable low-resistance line is controlled in a thickness direction of the base by controlling an intensity of the electric field through the gate. 
     
     
         9 . The non-volatile memory device of  claim 1 , wherein a size of the variable low-resistance line is controlled by controlling an application time of the electric field through the gate. 
     
     
         10 . The non-volatile memory device of  claim 1 , wherein the base comprises a ferroelectric material. 
     
     
         11 . The non-volatile memory device of  claim 1 , wherein the variable low-resistance line is maintained even when the electric field applied through the gate is removed. 
     
     
         12 . An operating method of a non-volatile memory device comprising: a base comprising a spontaneous polarizable material; a gate arranged adjacent to a surface of the base; and a source and a drain arranged apart from the gate and to contact the base, wherein the operating method includes:
 forming, in the base, a first region having a polarization in a first direction;   forming a second region that is adjacent to the gate of the first region and has a polarization in a second direction opposite to the first direction, by applying a first voltage to the base through the gate; and   forming a variable low-resistance line that is located between the first region and the second region and is electrically connected to the source and the drain, by growing the second region by maintaining the first voltage in the base for a first period of time through the gate,   the variable low-resistance line electrically connects the source to the drain,   the variable low-resistance line is located around the gate in a surface direction of the base.   
     
     
         13 . The operating method of  claim 12 , further comprising:
 converting the second region adjacent to the gate into the first region having the polarization in the first direction by applying a second voltage to the base through the gate; and   allowing the first region to pass by the variable low-resistance line by growing the first region by maintaining the second voltage in the base for a second period time through the gate.   
     
     
         14 . The operating method of  claim 13 , wherein the second voltage is different from the first voltage. 
     
     
         15 . The operating method of  claim 13 , wherein the second period of time is equal to or longer than the first period of time. 
     
     
         16 . The operating method of  claim 12 , wherein the variable low-resistance line is maintained even when application of the first voltage to the gate ends.