Method and circuit for power consumption reduction in active phase shifters

Abstract

An electronic circuit and method are provided. The electronic circuit includes an amplifier including first cascode branch and a second cascode branch, the amplifier being configured to receive a differential input and control signals, control gate voltages in the first cascode branch and gate voltages in the second cascode branch, generate a first output signal with the first cascode branch, and generate a second output signal with the second cascode branch, and a coupler configured to perform a summation of the first output signal and the second output signal, and generate a final phase shifted output, wherein the first cascode branch or the second cascode branch includes a first cascode arm and a second cascode arm.

What is claimed is: 
     
         1 . An electronic circuit, comprising:
 an amplifier including first cascode branch and a second cascode branch, the amplifier being configured to:   receive a differential input and control signals;   control gate voltages in the first cascode branch and gate voltages in the second cascode branch;   generate a first output signal with the first cascode branch; and   generate a second output signal with the second cascode branch; and   a coupler configured to:
 perform a summation of the first output signal and the second output signal; and 
   generate a final phase shifted output,
 wherein the first cascode branch or the second cascode branch includes a first cascode arm and a second cascode arm. 
   
     
     
         2 . The electronic circuit of  claim 1 ,
 wherein the coupler is a quadrature coupler,   wherein the amplifier is an in-phase (I) quadrature (Q) amplifier, and   wherein the first cascode branch is an I cascode branch including a first cascode arm and a second cascode arm.   
     
     
         3 . The electronic circuit of  claim 2 ,
 wherein the first cascode arm of the I cascode branch includes a first cascode transistor and a second cascode transistor, and the second cascode arm of the I cascode branch includes a third cascode transistor and a fourth cascode transistor.   
     
     
         4 . The electronic circuit of  claim 3 ,
 wherein the first, second, third and fourth cascode transistors of the I cascode branch are processed with I-based control signals of the received control signals and are segmented and weighted to produce relative I:Q ratios.   
     
     
         5 . The electronic circuit of  claim 2 ,
 wherein the second cascode branch is a Q cascode branch including a first cascode arm and a second cascode arm.   
     
     
         6 . The electronic circuit of  claim 5 ,
 wherein the first cascode arm of the Q cascode branch includes a first cascode transistor and a second cascade transistor, and the second cascode arm of the Q cascade branch includes a third cascade transistor and a fourth cascode transistor.   
     
     
         7 . The electronic circuit of  claim 6 ,
 wherein the first, second, third and fourth cascode transistors of the I cascade branch process Q-based control signals of the received control signals and are segmented and weighted to produce relative I:Q ratios.   
     
     
         8 . The electronic circuit of  claim 2 ,
 wherein the gate voltages are controlled based on the control signals, and   wherein the summation of the first and second output signals is a quadrature summation.   
     
     
         9 . A method, comprising:
 receiving, with an amplifier including a first cascode branch and a second cascode branch, a differential input and control signals;   controlling gate voltages in the first cascode branch and gate voltages in the second cascode branch;   generating, with the first cascode branch, a first output signal;   generating, with the second cascode branch, a second output signal;   performing, with a coupler, a summation of the first output signal and the second output signal; and   generating, with the coupler, a final phase shifted output,   wherein the first cascode branch or the second cascode branch includes a first cascode arm and a second cascode arm.   
     
     
         10 . The method of  claim 9 ,
 wherein the coupler is a quadrature coupler,   wherein the amplifier is an in-phase (I) quadrature (Q) amplifier, and   wherein the first cascode branch is an I cascode branch including a first cascode arm and a second cascode arm.   
     
     
         11 . The method of  claim 10 ,
 wherein the first cascode arm of the I cascode branch includes a first cascode transistor and a second cascode transistor, and the second cascode arm of the I cascode branch includes a third cascade transistor and a fourth cascode transistor.   
     
     
         12 . The method of  claim 11 ,
 wherein the first, second, third and fourth cascode transistors of the I cascode branch process I-based control signals of the received control signals and are segmented and weighted to produce relative ratios.   
     
     
         13 . The method of  claim 10 ,
 wherein the second cascode branch is a Q cascode branch including a first cascode arm and a second cascade arm.   
     
     
         14 . The method of  claim 13 ,
 wherein the first cascode arm of the Q cascode branch includes a first cascode transistor and a second cascode transistor, and the second cascode arm of the Q cascode branch includes a third cascade transistor and a fourth cascode transistor.   
     
     
         15 . The method of  claim 14 ,
 wherein the first, second, third and fourth cascode transistors of the Q cascade branch process Q-based control signals of the received control signals and are segmented and weighted to produce relative I:Q ratios.   
     
     
         16 . The method of  claim 9 ,
 wherein the gate voltages are controlled based on the control signals, and   wherein the summation of the first and second output signals is a quadrature summation.