Floating point multiply hardware using decomposed component numbers

Abstract

A processor system comprises one or more logic units configured to receive a processor instruction identifying a first floating point number to be multiplied with a second floating point number. The floating point numbers are each decomposed into a group of a plurality of component numbers, wherein a number of bits used to represent each floating point number is greater than a number of bits used to represent any component number in each group of the plurality of component numbers. The component numbers of the first group are multiplied with the component numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.

What is claimed is: 
     
         1 . A system, comprising:
 one or more logic units configured to:
 receive an indication of a first floating point number to be multiplied with a second floating point number, wherein the first floating point number and the second floating point number are identified in a processor instruction; 
 determine whether the first floating number is in a format represented by a number of bits that exceeds a maximum number of bits supported by hardware floating point capabilities of one or more multiplication units; 
 in response to a determination that the first floating point number is in the format that exceeds the hardware floating point capabilities of the one or more multiplication units, decompose the first floating point number that represents a single floating point number into a first group of a plurality of decomposed floating point numbers in a format supported by the hardware floating point capabilities of the one or more multiplication units; and 
 decompose the second floating point number that represents a single floating point number into a second group of a plurality of decomposed floating point numbers in the second format supported by the hardware floating point capabilities of the one or more multiplication units; and 
   the one or more multiplication units configured to:
 multiply the decomposed floating point numbers of the first group with the decomposed floating point numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number. 
   
     
     
         2 . The system of  claim 1 , wherein each of the one or more multiplication units is a 21-bit floating point unit. 
     
     
         3 . The system of  claim 2 , wherein the 21-bit floating point unit utilizes 1 bit for a sign bit, 9 bits for an exponent component, and 11 bits for a mantissa component. 
     
     
         4 . The system of  claim 1 , wherein each of the one or more multiplication units is able to perform an FP16 and a BFloat16 floating point multiplication operation. 
     
     
         5 . The system of  claim 1 , wherein the first floating point number is a 32-bit floating-point number and wherein hardware capabilities of the one or more multiplication units do not support performing a 32-bit floating-point multiplication operation using only a single multiplication operation. 
     
     
         6 . The system of  claim 1 , further comprising a matrix compute engine that includes a plurality of vector units. 
     
     
         7 . The system of  claim 6 , wherein each of the plurality of vector units includes a vector multiply unit and a vector adder unit. 
     
     
         8 . The system of  claim 7 , wherein the vector multiply unit includes the one or more multiplication units. 
     
     
         9 . The system of  claim 7 , wherein the vector adder unit includes an adder tree. 
     
     
         10 . The system of  claim 1 , wherein a sum of each decomposed floating point number of the first group of the plurality of decomposed floating point numbers is equal to the first floating point number. 
     
     
         11 . The system of  claim 1 , wherein a mantissa component of at least one decomposed floating point number of the first group of the plurality of component numbers is normalized to remove leading zeros and a 1-bit binary integer. 
     
     
         12 . The system of  claim 1 , wherein the first group of the plurality of decomposed floating point numbers includes a first decomposed floating point number and a second decomposed floating point number, and wherein a sum of the first decomposed floating point number and the second decomposed floating point number is equal to the first floating point number. 
     
     
         13 . The system of  claim 12 , wherein the first decomposed floating point number is associated with 11-bits of a mantissa component of the first floating point number and the second decomposed floating point number is associated with a remaining 12-bits of the mantissa component of the first floating point number. 
     
     
         14 . The system of  claim 12 , wherein the first decomposed floating point number represents a most significant bit sequence of the first floating point number and the second decomposed floating point number represents a least significant bit sequence of the first floating point number, and wherein the most significant bit sequence is associated with a fewer number of bits of a mantissa component of the first floating point number than the least significant bit sequence 
     
     
         15 . The system of  claim 1 , wherein the one or more logic units are further configured to:
 prepare a first vector operand using one or more decomposed floating point numbers of the first group of the plurality of decomposed floating point numbers; and   prepare a second vector operand using one or more decomposed floating point numbers of the second group of the plurality of decomposed floating point numbers.   
     
     
         16 . The system of  claim 1 , wherein the result of multiplying the first floating point number with the second floating point number is used at least in part to apply a neural network model to an artificial intelligence problem. 
     
     
         17 . A method, comprising:
 receiving an indication of a first floating point number to be multiplied with a second is floating point number, wherein the first floating point number and the second floating point number are identified in a processor instruction;   determining whether the first floating number is in a format represented by a number of bits that exceeds a maximum number of bits supported by hardware floating point capabilities of one or more multiplication units;   in response to a determination that the first floating point number is in the format that exceeds the hardware floating point capabilities of the one or more multiplication units, decomposing the first floating point number that represents a single floating point number into a first group of a plurality of decomposed floating point numbers in a format supported by the hardware floating point capabilities of the one or more multiplication units; and   decomposing the second floating point number that represents a single floating point number into a second group of a plurality of decomposed floating point numbers in the second format supported by the hardware floating point capabilities of the one or more multiplication units; and   multiplying the decomposed floating point numbers of the first group with the decomposed floating point numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.   
     
     
         18 . The method of  claim 17 , wherein the first floating point number is a 32-bit floating-point number and wherein hardware capabilities of the one or more multiplication units do not support performing a 32-bit floating-point multiplication operation using only a single multiplication operation. 
     
     
         19 . The method of  claim 17 , further comprising:
 preparing a first vector operand using one or more decomposed floating point numbers of the first group of the plurality of decomposed floating point numbers; and   preparing a second vector operand using one or more decomposed floating point numbers of the second group of the plurality of decomposed floating point numbers.   
     
     
         20 . A computer program product, the computer program product being embodied in a non-transitory computer readable storage medium and comprising computer instructions for:
 receiving an indication of a first floating point number to be multiplied with a second floating point number, wherein the first floating point number and the second floating point number are identified in a processor instruction;   determining whether the first floating number is in a format represented by a number of bits that exceeds a maximum number of bits supported by hardware floating point capabilities of one or more multiplication units;   in response to a determination that the first floating point number is in the format that exceeds the hardware floating point capabilities of the one or more multiplication units, decomposing the first floating point number that represents a single floating point number into a first group of a plurality of decomposed floating point numbers in a format supported by the hardware floating point capabilities of the one or more multiplication units; and   decomposing the second floating point number that represents a single floating point number into a second group of a plurality of decomposed floating point numbers in the second format supported by the hardware floating point capabilities of the one or more multiplication units; and   multiplying the decomposed floating point numbers of the first group with the decomposed floating point numbers of the second group to determine intermediate multiplication results that are summed together to determine an effective result that represents a result of multiplying the first floating point number with the second floating point number.