Semiconductor structure and manufacture method thereof

Abstract

A method of making a semiconductor structure can include: (i) forming a plurality of oxide layers on a semiconductor substrate; (ii) forming a plurality of conductor layers on the plurality of oxide layers; (iii) forming plurality of thickening layers on the plurality of conductor layers; (iv) patterning the plurality of conductor layers and the plurality of thickening layers to form a hard mask; and (v) implanting ion using the hard mask to form a plurality of doped regions.

1 .- 18 . (canceled) 
     
     
         19 . A method of making a semiconductor structure, the method comprising:
 a) forming a first oxide layer on a first region of a semiconductor substrate and forming a second oxide layer on a second region of a semiconductor substrate;   b) forming a first gate structure on the first region of the semiconductor substrate, and forming a second gate structure on the second region of the semiconductor substrate, wherein the forming the first and second gate structures comprises forming a polysilicon layer on the first and second oxide layers, forming a thickening layer on the polysilicon layer, and patterning the thickening layer to form a patterned thickening layer located only in the first region, and to expose the polysilicon layer in the second region using a mask layer; and   c) forming a plurality of doped regions by implanting ions into the semiconductor substrate using the first gate structure as a first hard mask on the first region and the second gate structure as a second hard mask on the second region.   
     
     
         20 . The method of  claim 19 , further comprising:
 a) etching the patterned thickening layer in the first region and patterning the polysilicon layer remaining in the first region to respectively form an etched thickening layer and a first conductor layer, wherein the first hard mask comprises the first conductor layer; and   b) patterning the polysilicon layer in the second region to form a second conductor layer, wherein the second hard mask comprises the second conductor layer.   
     
     
         21 . The method of  claim 20 , wherein the first conductor layer is configured as a first gate conductor, and wherein the second conductor layer is configured as a second gate conductor. 
     
     
         22 . The method of  claim 20 , wherein the etched thickening layer comprises a metal silicide layer. 
     
     
         23 . The method of  claim 20 , wherein the first conductor layer and the etched thickening layer form a composite gate conductor. 
     
     
         24 . The method of  claim 22 , wherein the thickening layer further comprises an antireflection layer on the metal silicide layer. 
     
     
         25 . The method of  claim 21 , wherein the forming the first and second gate conductors comprises:
 c) etching the thickening layer in the second region to expose the polysilicon layer in the second region;   d) etching the polysilicon layer in the second region on a predetermined portion of the second oxide layer to form the second gate conductor; and   e) etching the thickening layer and the polysilicon layer in the first region on a predetermined portion of the first oxide layer to form the first gate conductor.   
     
     
         26 . The method of  claim 19 , further comprising doping a portion of the polysilicon layer to regulate a work function. 
     
     
         27 . The method of  claim 20 , wherein the second conductor layer and the second oxide layer combined is thinner than the thickening layer, the first conductor layer, and the first oxide layer combined. 
     
     
         28 . The method of  claim 19 , wherein the formation of the first oxide layer and second oxide layer comprises:
 a) forming a first oxide layer of a first thickness on a semiconductor substrate;   b) forming a first region mask to cover a first region of the semiconductor substrate, and to expose a second region of the semiconductor substrate;   c) etching the first oxide layer on the second region of the semiconductor substrate;   d) removing the first region mask; and   e) employing an oxidation process to grow a second oxide layer of a second thickness on the second region, resulting in the thickness of the first oxide layer being increased to a third thickness, wherein the second thickness is less than the first thickness.   
     
     
         29 . A semiconductor structure, comprising:
 a) a semiconductor substrate;   b) a first oxide layer and a second oxide layer on the semiconductor substrate;   c) a first semiconductor device in a first region of the semiconductor substrate, wherein the first semiconductor device comprises the first oxide layer and a first gate conductor on the first oxide layer, and wherein the first gate conductor comprises a conductor layer; and   d) a second semiconductor device in a second region of the semiconductor substrate, wherein the second semiconductor device comprises the second oxide layer and a second gate conductor on the second oxide layer, and wherein the second gate conductor comprises a conductor layer and a silicide layer.   
     
     
         30 . The semiconductor structure of  claim 29 , wherein the conductor layer comprises a polysilicon layer, and the silicide layer comprises a metal silicide layer. 
     
     
         31 . The semiconductor structure of  claim 29 , further comprising an antireflection layer on the metal silicide layer. 
     
     
         32 . The semiconductor structure of  claim 29 , wherein the first gate conductor is doped. 
     
     
         33 . The semiconductor structure of  claim 31 , wherein the antireflection layer comprises an oxide layer. 
     
     
         34 . The semiconductor structure of  claim 29 , wherein the first semiconductor device comprises first doped regions located in the semiconductor substrate and at two side of the first gate conductor, and the second semiconductor device comprises second doped regions located in the semiconductor substrate and at the first gate conductor. 
     
     
         35 . The semiconductor structure of  claim 34 , further comprising shallow trench isolation between the first doped regions and second doped regions.