Isolation in integrated circuit devices

Abstract

Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.

1 . An integrated circuit (IC) device, comprising:
 a first structure on a base, wherein the first structure has a width that is 4 nanometers or less;   a second structure on the base, wherein the second structure has a width that is 4 nanometers or less;   a trench bounded by the first structure, the second structure, and the base, wherein the trench has a height-to-width aspect ratio greater than or equal to 4:1; and   a dielectric layer that fills at least a bottom portion of the trench.   
     
     
         2 . The IC device of  claim 1 , wherein the first structure is a first fin and the second structure is a second fin. 
     
     
         3 . The IC device of  claim 2 , wherein the first fin is a semiconductor fin, the second fin is a semiconductor fin, and the first fin, the second fin, and the base have a same semiconductor composition. 
     
     
         4 . The IC device of  claim 2 , wherein the first fin includes multiple different material layers, and the second fin includes multiple different material layers. 
     
     
         5 . The IC device of  claim 2 , further comprising:
 a first gate on the first fin; and   a second gate on the second fin.   
     
     
         6 . The IC device of  claim 5 , further comprising a pair of spacers abutting the first gate, the pair of spacers separating the first gate from the dielectric layer. 
     
     
         7 . The IC device of  claim 1 , wherein the trench has a width of 30 nanometers or less. 
     
     
         8 . The IC device of  claim 1 , wherein the dielectric layer includes an oxide, a nitride, or a carbide. 
     
     
         9 . The IC device of  claim 1 , wherein the dielectric layer includes a first dielectric portion that is conformal over the first structure and the second structure, and a second dielectric portion on the first dielectric portion. 
     
     
         10 . The IC device of  claim 9 , wherein the first dielectric portion and the second dielectric portion have different material compositions. 
     
     
         11 . The IC device of  claim 9 , wherein the first dielectric portion has a thickness between 1 nanometer and 4 nanometers. 
     
     
         12 . The IC device of  claim 1 , wherein the dielectric layer fills a bottom portion of the trench, and a portion of the first structure and a portion of the second structure extend above a top of the dielectric layer. 
     
     
         13 . A computing device, comprising:
 a processing device including a first transistor and a second transistor, wherein the first transistor includes at least a portion of a first fin, the first fin has a width that is 4 nanometers or less, the second transistor includes at least a portion of a second fin, the second fin has a width that is 4 nanometers or less, the first transistor and the second transistor define a trench therebetween, the trench has a height-to-width aspect ratio greater than or equal to 4:1, and a dielectric layer fills at least a bottom portion of the trench; and   a memory device, communicatively coupled to the processing device.   
     
     
         14 . The computing device of  claim 13 , wherein the first fin and the second fin extend from a semiconductor substrate. 
     
     
         15 . The computing device of  claim 14 , wherein the first fin is a semiconductor fin, the second fin is a semiconductor fin, and the first fin, the second fin, and the base have a same semiconductor composition. 
     
     
         16 . The computing device of  claim 13 , further comprising:
 a first gate on the first fin; and   a second gate on the second fin.   
     
     
         17 . The computing device of  claim 16 , further comprising a pair of spacers abutting the first gate, the pair of spacers separating the first gate from the dielectric layer. 
     
     
         18 . The computing device of  claim 13 , wherein the dielectric layer includes a first dielectric portion that is conformal over the first fin and the second fin, and a second dielectric portion on the first dielectric portion. 
     
     
         19 . The computing device of  claim 18 , wherein the first dielectric portion and the second dielectric portion have different material compositions. 
     
     
         20 . The computing device of  claim 18 , wherein the first dielectric portion has a thickness between 1 nanometer and 4 nanometers.