US2022148981A1PendingUtilityA1
Integrated circuit package with through void guard trace
Est. expiryMar 23, 2038(~11.7 yrs left)· nominal 20-yr term from priority
H10W 20/493H10W 90/724H10W 44/00H10W 42/00H10W 70/685H01L 23/564H01L 23/5256
62
PatentIndex Score
0
Cited by
0
References
0
Claims
Abstract
Apparatuses, systems and methods associated with over void signal trace design are disclosed herein. In embodiments, an integrated circuit (IC) package may include a first layer that has a void and a guard trace, wherein a first portion of the void is located on a first side of the guard trace and a second portion of the void is located on a second side of the guard trace. The IC package may further include a second layer located adjacent to the first layer, wherein the second layer has a signal trace that extends along the guard trace. Other embodiments may be described and/or claimed.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . An integrated circuit (IC) package, comprising:
a first layer that has a void and a first trace, wherein a first portion of the void is located on a first side of the first trace and a second portion of the void is located on a second side of the first trace, and wherein the first trace has a width; and a second layer located adjacent to the first layer, wherein the second layer has a second trace that extends along the first trace, and wherein the second trace has a width less than the width of the first trace.
2 . The IC package of claim 1 , wherein the first portion of the void has a first widest width, and the second portion of the void has a second widest width greater than the first widest width.
3 . The IC package of claim 1 , further comprising a dielectric material located between the first trace and second trace, wherein the dielectric material separates the second trace from the first trace.
4 . The IC package of claim 1 , wherein the first trace is at least twice as wide as the second trace.
5 . The IC package of claim 1 , wherein a width of the first trace is at least ten percent greater than a width of the second trace.
6 . The IC package of claim 1 , wherein a width of the second trace is between 40 and 60 micrometers, and wherein a width of the first trace is between 80 and 120 micrometers.
7 . The IC package of claim 6 , wherein a width of the void is greater than 200 micrometers.
8 . The IC package of claim 1 , wherein the IC package further includes a ground plane of a type of conductive metal, and wherein the first trace is of the type of conductive metal.
9 . The IC package of claim 8 , wherein the void is encircled by the ground plane.
10 . The IC package of claim 1 , wherein the void is an adhesion void.
11 . The IC package of claim 1 , wherein the second trace is to be utilized for transmission of a high-speed signal.
12 . A computer device, comprising:
a circuit board; and an integrated circuit (IC) package mounted to the circuit board, wherein the IC package includes:
a first layer that has a void and a first trace, wherein a first portion of the void is located on a first side of the first trace and a second portion of the void is located on a second side of the first trace, and wherein the first trace has a width; and
a second layer located adjacent to the first layer, wherein the second layer has a second trace that extends along the first trace, and wherein the second trace has a width less than the width of the first trace.
13 . The computer device of claim 12 , wherein the first portion of the void has a first widest width, and the second portion of the void has a second widest width greater than the first widest width.
14 . The computer device of claim 12 , wherein the IC package further includes a dielectric material located between the first trace and second trace, and wherein the dielectric material isolates the second trace from the first trace.
15 . The computer device of claim 12 , wherein the first trace is at least twice as wide as the second trace.
16 . The computer device of claim 12 , wherein a width of the first trace is at least ten percent greater than a width of the second trace.
17 . The computer device of claim 12 , wherein a width of the second trace is between 40 and 60 micrometers, and wherein a width of the first trace is between 80 and 120 micrometers.
18 . The computer device of claim 17 , wherein a width of the void is greater than 200 micrometers.
19 . The computer device of claim 12 , wherein the IC package further includes a ground plane of a type of conductive metal, and wherein the first trace is of the type of conductive metal.
20 . The computer device of claim 19 , wherein the void is encircled by the ground plane.
21 . The computer device of claim 12 , wherein the void is an adhesion void.
22 . The computer device of claim 12 , wherein the second trace is to be utilized for transmission of a high-speed signal.
23 . A substrate for an integrated circuit package, comprising:
a first layer that has a void and a first trace, wherein a first portion of the void is located on a first side of the first trace and a second portion of the void is located on a second side of the first trace, and wherein the first trace has a width; and a second layer located adjacent to the first layer, wherein the second layer has a second trace that extends along the first trace, and wherein the second trace has a width less than the width of the first trace.
24 . The substrate of claim 23 , wherein the first portion of the void has a first widest width, and the second portion of the void has a second widest width greater than the first widest width.
25 . The substrate of claim 23 , further comprising a dielectric material located between the first trace and second trace, wherein the dielectric material separates the second trace from the first trace.Join the waitlist — get patent alerts
Track US2022148981A1 — get alerts on status changes and closely related new filings.
We store only your email — no account needed. See our privacy policy.