Memory-based distributed processor architecture

Abstract

Distributed processors and methods for compiling code for execution by distributed processors are disclosed. In one implementation, a distributed processor may include a substrate; a memory array disposed on the substrate; and a processing array disposed on the substrate. The memory array may include a plurality of discrete memory banks, and the processing array may include a plurality of processor subunits, each one of the processor subunits being associated with a corresponding, dedicated one of the plurality of discrete memory banks. The distributed processor may further include a first plurality of buses, each connecting one of the plurality of processor subunits to its corresponding, dedicated memory bank, and a second plurality of buses, each connecting one of the plurality of processor subunits to another of the plurality of processor subunits.

1 - 27 . (canceled) 
     
     
         28 . A distributed processor on a chip, comprising:
 a semiconductor substrate;   a memory array disposed on the semiconductor substrate, the memory array including a plurality of discrete memory banks;   a processing array disposed on the semiconductor substrate, the processing array including a plurality of processor subunits, each one of the processor subunits being associated with one or more corresponding, dedicated discrete memory banks from among the plurality of discrete memory banks,   wherein, based on an instruction received at the chip from a host external to the chip, each of the plurality of processor subunits is configured to respond by:
 retrieving data stored in its one or more corresponding, dedicated discrete memory banks, 
 performing one or more calculations using the retrieved data, and 
 writing a result of the performed one or more calculations to its one or more corresponding, dedicated discrete memory banks; and 
   a first plurality of buses, each connecting one of the plurality of processor subunits to its one or more corresponding, dedicated discrete memory banks.   
     
     
         29 . The distributed processor on the chip of  claim 28 , wherein the plurality of processor subunits of the processing array are spatially distributed among the plurality of discrete memory banks of the memory array. 
     
     
         30 . The distributed processor on the chip of  claim 28 , wherein the distributed processor on a chip is an artificial intelligence accelerator processor. 
     
     
         31 . The distributed processor on the chip of  claim 28 , wherein each of the plurality of processor subunits is configured to execute software code associated with a particular application independently relative to other processor subunits among the plurality of processor subunits. 
     
     
         32 . The distributed processor on the chip of  claim 28 , wherein the plurality of processor subunits are arranged in at least one row and at least one column. 
     
     
         33 . The distributed processor on the chip of  claim 28 , wherein the plurality of processor subunits are arranged in a star pattern. 
     
     
         34 . The distributed processor on the chip of  claim 28 , wherein each processor subunit is associated with at least two corresponding, dedicated discrete memory banks. 
     
     
         35 . The distributed processor on the chip of  claim 28 , wherein each dedicated discrete memory bank comprises at least one dynamic random access memory.