Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill

Abstract

Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.

We claim: 
     
         1 . A semiconductor die assembly, comprising:
 a first semiconductor die having a central region and a lateral region;   a die stack having one or more second semiconductor dies carried by the central region of the first semiconductor die;   an adhesive over at least a portion of the outer region of the first die, wherein the adhesive includes a vent channel extending from an external surface of the adhesive to an internal surface adjacent the die stack;   a heat transfer structure at least partially carried by the lateral region of the first semiconductor die; and   an underfill material between the heat transfer structure and the die stack.   
     
     
         2 . The semiconductor die assembly of  claim 1  wherein the heat transfer structure includes a planar lower surface attached to the adhesive. 
     
     
         3 . The semiconductor die assembly of  claim 1  wherein the die stack has a first longitudinal side and a second longitudinal side, and wherein the vent channel extends from the external surface of the adhesive to the internal surface adjacent the first longitudinal side. 
     
     
         4 . The semiconductor die assembly of  claim 3  wherein the heat transfer structure has a sidewall spaced apart from the first and second longitudinal sides of the die stack by a gap. 
     
     
         5 . The semiconductor die assembly of  claim 1  further comprising a lid carried by the heat transfer structure above the die stack. 
     
     
         6 . The semiconductor die assembly of  claim 1 , further comprising a package support substrate, wherein:
 the first semiconductor die is mounted to an upper surface the package support substrate;   the adhesive includes a first portion over the lateral region of the first semiconductor die and a second portion over the package substrate; and   the heat transfer structure is at least partially carried by the package substrate.   
     
     
         7 . The semiconductor die assembly of  claim 6  wherein the package support substrate includes a lower surface having a plurality of electrical connectors, and wherein the first semiconductor die is electrically coupled the plurality of electrical connectors. 
     
     
         8 . The semiconductor die assembly of  claim 1  wherein an upper die of the die stack has a top surface area, and wherein the heat transfer structure has an opening larger than the top surface area of the upper die. 
     
     
         9 . A semiconductor die assembly, comprising:
 a package substrate having a first surface and a second surface opposite the first surface;   a first die carried by the first surface of the package substrate, the first die having a stacking region and a lateral region outboard of the stacking region;   a die stack having one or more second dies carried by the stacking region, the die stacking having an uppermost surface with a surface area;   a thermal transfer structure attached to the lateral region of the first die and the package substrate, wherein the thermal transfer structure has an opening larger than the surface area of the uppermost surface; and   an underfill material between the thermal transfer structure and the die stack, the underfill material covering sides of the die stack up to at least the uppermost surface of the die stack.   
     
     
         10 . The semiconductor die assembly of  claim 9  wherein the thermal transfer structure extends to a height above an elevation of the uppermost surface of the die stack. 
     
     
         11 . The semiconductor die assembly of  claim 9  wherein the thermal transfer structure includes a sidewall defining a cavity, and wherein the die stack is positioned in the cavity. 
     
     
         12 . The semiconductor die assembly of  claim 11  wherein the die stack includes two or more second dies, and wherein the die stack includes thermally conductive elements positioned between and electrically isolated from each of the two or more second dies. 
     
     
         13 . The semiconductor die assembly of  claim 9  wherein the thermal transfer structure includes a planar lower surface attached to the lateral region of the first die and the package substrate by a continuous adhesive. 
     
     
         14 . The semiconductor die assembly of  claim 9 , further comprising an adhesive attaching the thermal transfer structure to the lateral region of the first die and the package substrate, wherein the adhesive includes a vent channel extending from an external sidewall of the adhesive to an internal sidewall. 
     
     
         15 . The semiconductor die assembly of  claim 9 , further comprising a lid at least partially carried by the thermal transfer structure. 
     
     
         16 . The semiconductor die assembly of  claim 15  wherein the lid is at least partially carried by the uppermost surface of the die stack. 
     
     
         17 . The semiconductor die assembly of  claim 9  wherein the die stack is electrically coupled to the first die via one or more conductive elements positioned between the die stack and the first semiconductor die. 
     
     
         18 . The semiconductor die assembly of  claim 9  wherein the die stack includes two or more second dies, wherein each of the two or more second dies in the die stack is separated by a space, and wherein the underfill material fills the space between each of the two or more second dies in the die stack. 
     
     
         19 . A stacked semiconductor die assembly, comprising:
 a first die having an upper surface with a central portion and a peripheral region outboard of the central region;   a die stack having one or more second dies carried by the central region of the upper surface of the first die;   a thermally conductive frame attached to the lateral region of the upper surface of the first die, wherein the thermally conductive frame includes a cavity having a longitudinal footprint larger than the die stack, and wherein the thermal; and   an underfill material filling the cavity to an elevation at or above an upper surface of the die stack.   
     
     
         20 . The stacked semiconductor die assembly of  claim 19  further comprising an adhesive attaching the thermally conductive frame to the peripheral region of the first die, wherein the adhesive includes a vent channel extending from an external sidewall of the adhesive to an internal sidewall.