Method of optimizing scalar register allocation and a system thereof

Abstract

The present disclosure relates to a system and a method of optimizing scalar register allocation by a processor. The method comprises receiving an intermediate code and information about one or more available physical registers in a memory of the processor, as input. The method further comprises allocating one or more virtual registers based on the received information, wherein each virtual register is having size of each available physical register. The method also comprises mapping one or more groups of 8-bit location of the one or more virtual registers to one or more register classes. The method further comprises identifying a plurality of scalar variables from the input intermediate code, and dynamically assigning the one or more available physical registers to the identified scalar variables using the one or more register classes.

We claim: 
     
         1 . A method of optimizing scalar register allocation by a processor, comprising:
 receiving an intermediate code and information about one or more available physical registers in a memory of the processor, as input;   allocating one or more virtual registers based on the received information, wherein each virtual register is having size of each of the one or more available physical register;   mapping one or more groups of 8-bit location of the one or more virtual registers to one or more register classes;   identifying a plurality of scalar variables from the input intermediate code; and   dynamically assigning the one or more available physical registers to the identified plurality of scalar variables using the one or more register classes.   
     
     
         2 . The method as claimed in  claim 1 , wherein each of the one or more register classes include different data types, each data type having different size. 
     
     
         3 . The method as claimed in  claim 1 , wherein mapping one or more groups of 8-bit location of the one or more virtual registers to one or more register classes is based on a size of the available physical registers. 
     
     
         4 . The method as claimed in  claim 1 , wherein assigning the one or more available physical registers comprises:
 allocating the one or more register classes to the identified scalar variables, wherein the one or more register classes are allocated based on associated computer hardware, type of scalar variables, and number of the available physical registers; and   assigning the one or more available physical registers to each of the identified scalar variables, based on the allocated one or more register classes and type of scalar variable.   
     
     
         5 . The method as claimed in  claim 4 , wherein allocating the one or more register classes to the identified scalar variables comprises allocating greedily first available continuous one or more groups of 8-bit locations based on a data type associated with each identified scalar variable, wherein the data type is one of byte, short, int, long, char, float, and double. 
     
     
         6 . A system to optimize scalar register allocation, the system comprising:
 a memory; and   a processor, coupled to the memory, and configured to:
 receive an intermediate code and information about one or more available physical registers in the memory of the processor, as input; 
 allocate one or more virtual registers based on the received information, wherein each virtual register is having size of each available physical register; 
 map one or more groups of 8-bit location of the one or more virtual registers to one or more register classes; 
 identify the plurality of scalar variables from the input intermediate code; and 
 dynamically assign the one or more available physical registers to the identified scalar variables using the one or more register classes. 
   
     
     
         7 . The system as claimed in  claim 6 , wherein the processor is configured to map the one or more groups of 8-bit location to the one or more register classes that include different data types, wherein each data type having different sizes. 
     
     
         8 . The system as claimed in  claim 6 , wherein the processor is configured to map the one or more groups of 8-bit location of the one or more virtual registers to the one or more register classes based on a size of the available physical registers. 
     
     
         9 . The system as claimed in  claim 6 , wherein to assign the one or more available registers, the processor is configured to:
 allocate the one or more register classes to the identified scalar variables, wherein the one or more register classes are allocated based on associated computer hardware, type of scalar variables, and number of the available physical registers; and   assign the one or more available physical registers to each of the identified scalar variables, based on the allocated one or more register classes and type of scalar variable.   
     
     
         10 . The system as claimed in  claim 9 , wherein to allocate the one or more register classes to the identified scalar variables, the processor is configured to allocate greedily first available continuous one or more groups of 8-bit locations based on a data type associated with each identified scalar variable, wherein the data type is one of byte, short, int, long, char, float, and double. 
     
     
         11 . A non-transitory computer readable medium comprising instructions that, when executed, cause one or more processors to:
 receive an intermediate code and information about one or more available physical registers in a memory of the processor, as input;   allocate one or more virtual registers based on the received information, wherein each virtual register is having size of each of the one or more available physical register;   map one or more groups of 8-bit location of the one or more virtual registers to one or more register classes;   identify a plurality of scalar variables from the input intermediate code; and   dynamically assign the one or more available physical registers to the identified plurality of scalar variables using the one or more register classes.   
     
     
         12 . The non-transitory computer readable medium as claimed in  claim 11 , wherein the one or more processors is configured to map the one or more groups of 8-bit location to the one or more register classes that include different data types, wherein each data type having different sizes. 
     
     
         13 . The non-transitory computer readable medium as claimed in  claim 11 , wherein the one or more processors is configured to map the one or more groups of 8-bit location of the one or more virtual registers to the one or more register classes based on a size of the available physical registers. 
     
     
         14 . The non-transitory computer readable medium of  claim 11 , wherein the one or more processors assign the one or more available physical registers by performing steps comprising:
 allocating the one or more register classes to the identified scalar variables, wherein the one or more register classes are allocated based on associated computer hardware, type of scalar variables, and number of the available physical registers; and   assigning the one or more available physical registers to each of the identified scalar variables, based on the allocated one or more register classes and type of scalar variable.   
     
     
         15 . The non-transitory computer readable medium of  claim 13 , wherein the one or more processors is configured to allocate the one or more register classes to the identified scalar variables by allocating greedily first available continuous one or more groups of 8-bit locations based on a data type associated with each identified scalar variable, wherein the data type is one of byte, short, int, long, char, float, and double.